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| user? manual printed in japan document no. u12790ej2v0ud00 (2nd edition) date published october 2003 n cp(k) printed in japan pd178076 pd178078 pd178096a pd178098a pd178f098 1998, 2003 pd178078, 178098a subseries 8-bit single-chip microcontrollers
2 user? manual u12790ej2v0ud [memo] 3 user? manual u12790ej2v0ud notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. 4 user? manual u12790ej2v0ud iebus is a trademark of nec electronics corporation. windows and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. tron stands for the realtime operating system nucleus. itron is an abbreviation of industrial tron. these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. 5 user s manual u12790ej2v0ud the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. purchase of nec electronics i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. the information in this document is current as of march, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": 6 user s manual u12790ej2v0ud regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j03.4 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 sucursal en espa ? a madrid, spain tel: 091-504 27 87 v ? lizy-villacoublay, france tel: 01-30-67 58 00 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 tyskland filial taeby, sweden tel: 08-63 80 820 united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: 7 user? manual u12790ej2v0ud major revision in this edition (1/2) page description throughout addition of pd178096a and 178098a modification of pd178f098 from under development to developed p.35 modification of 1.5 development of 8-bit dts series p.48 modification of pin handling in 2.2.26 v pp ( pd178f098 only) pp.50 to 53 modification of table 2-1 pin i/o circuit types and figure 2-1 pin i/o circuits p.59 addition of description of programming area in 3.1.2 internal data memory space pp.66 and 67 modification of figure 3-10 data to be saved to stack memory and figure 3-11 data to be restored from stack memory p.82 modification of [example] in 3.4.4 short direct addressing pp.85 to 87 addition of [illustration] to 3.4.7 based addressing , 3.4.8 based indexed addressing , and 3.4.9 stack addressing p.109 addition of description of output latches after reset to 4.4 port function operations pp.122 and 123 6.2 configuration of 16-bit timer/event counter 0 ?addition of cautions to (2) 16-bit capture/compare register 00 (cr00) ?addition of table 6-3 cr01 capture trigger and valid edge of ti00 pin (crc02 = 1) ?addition of caution to (3) 16-bit capture/compare register 01 (cr01) p.128 addition of caution to figure 6-5 format of prescaler mode register 0 (prm0) p.144 6.4.5 one-shot pulse output operation ?modification of figure 6-26 timing of one-shot pulse output operation with software trigger ?addition of note to (2) one-shot pulse output with external trigger pp.149 to 155 addition of 6.5 program list p.157 addition of (6) (c) one-shot pulse output function to 6.6 notes on 16-bit timer/event counter 0 pp.163 and 164 7.2 configuration of 8-bit timer/event counters 50 and 51 ?addition of note to (1) 8-bit timer counters 50 and 51 (tm50 and tm51) ?addition of description of pwm mode to (2) 8-bit compare registers 50 and 51 (cr50 and cr51) pp.181 to 183 addition of 7.5 program list p.215 addition of (4) noise countermeasures and (6) input impedance of ani0 to ani7 pins to 11.5 a/d converter cautions p.348 addition of figure 16-2 block diagram of baud rate generator p.361 a ddition of caution to figure 16-6 permissible error of baud rate allowing for sampling error (k = 0) pp.369 and 382 addition of caution about inversion of iebus protocol and signal inside the microcontroller to 17.1.6 transfer format of iebus and 17.1.8 bit format pp.378 and 379 modification of note and caution in 17.1.6 (9) acknowledge bit p.382 addition of description of lock setting conditions and lock release conditions to 17.1.7 (4) locking and unlocking p.382 addition of description of timing error detection for each period to 17.1.8 bit format p.383 addition of notes about automatic master reprocessing to table 17-7 comparison of existing and simple iebus interface functions pp.387 to 389, 17.4.2 description of internal registers 391, 392, and ?explanation of each register thoroughly modified and note added 394 to 399 ?addition of figures of interrupt timing to figures 17-16 to 17-19 ?addition of figure 17-23 example of broadcast communication flag operation ?addition of table 17-9 reset conditions of flags in isr register 8 user? manual u12790ej2v0ud major revision in this edition (2/2) page description pp.406, 408, and 17.5 interrupt operations of iebus controller 409 ?thorough modification of contents ?addition of 17.5.3 communication error source processing list p.413 addition of description of wait of slave unit to 17.6.2 master reception p.459 correction of description of drive type of eo1 pin in 19.4.1 operation of each block of pll frequency synthesizer p.488 correction of note in table 22-1 hardware status after reset p.496 thorough modification of descriptions of flash memory programming as 23.3 flash memory features pp.520 to 538 addition of chapter 25 electrical specifications p.539 addition of chapter 26 package drawing p.540 addition of chapter 27 recommended soldering conditions pp.541 to 551 thorough modification of descriptions in appendix a development tools deletion of embedded software pp.552 to 557 addition of appendix b register index pp.558 and 559 addition of appendix c revision history the mark shows major revised points. 9 user? manual u12790ej2v0ud preface readers this manual has been prepared for user engineers who want to understand the functions of the pd178078 and 178098a subseries in order to design and develop its application systems and programs. purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the pd178078 and 178098a subseries manual is separated into two parts: this manual and the instruction edition (common to the 78k/0 series). pd178078, 178098a subseries user? manual pin functions cpu functions internal block functions instruction set interrupts explanation of each instruction other on-chip peripheral functions electrical specifications how to read this manual it is assumed that readers of this manual have general knowledge in the fields of electricity, logic circuits, and microcontrollers. to understand the functions in general: read this manual in the order of the contents. to know the pd178078, 178098a subseries instruction functions in detail: refer to the 78k/0 series instruction user? manual (u12326e) how to interpret the register format: the name is defined as a reserved word in the df178098 and ra78k 0, and is defined in the header file named sfrbit.h in the cc78k0 of a bit whose number is in angle brackets (<>). to know the electrical specifications of the pd178078, 178098a subseries: refer to chapter 25 electrical specifications . conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (overscore over pin or signal name) note: footnote for item marked with note in the text caution: information requiring particular attention remark: supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh 78k/0 series instruction user s manual 10 user? manual u12790ej2v0ud document name document no. ra78k0 assembler package operation u14445e language u14446e structured assembly language u11789e cc78k0 c compiler operation u14297e language u14298e sm78k series system simulator ver.2.30 or later operation (windows tm based) u15373e external part user open interface specifications u15802e id78k series integrated debugger ver.2.30 or later operation (windows based) u15185e rx78k0 real-time os fundamentals u11537e installation u11536e project manager ver.3.12 or later (windows based) u14610e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to pd178078, 178098a subseries document name document no. pd178078, 178098a subseries user? manual this manual 78k/0 series instruction user? manual u12326e 78k/0 series application note basics ( ) u12704e documents related to software development tools (user? manuals) 11 user s manual u12790ej2v0ud documents related to hardware development tools (user? manuals) document name document no. ie-78k0-ns in-circuit emulator u13731e ie-78k0-ns-a in-circuit emulator u14889e ie-78k0-ns-pa performance board u16109e ie-178098-ns-em1 emulation board u14013e ie-78001-r-a in-circuit emulator u14142e ie-78k0-r-ex1 in-circuit emulator to be prepared documents related to flash memory writing document name document no. pg-fp3 flash memory programmer user s manual u13502e pg-fp4 flash memory programmer user s manual u15260e other related documents document name document no. semiconductor selection guide - products and packages - x13769x semiconductor device mounting technology manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e note see the semiconductor device mount manual website (http://www.necel.com/pkg/en/mount/index.html). caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 12 user? manual u12790ej2v0ud contents chapter 1 outline ....................................................................................................................... 31 1.1 features .............................................................................................................................. 3 1 1.2 applications ....................................................................................................................... 32 1.3 ordering information ........................................................................................................ 32 1.4 pin configuration (top view) .......................................................................................... 33 1.5 development of 8-bit dts series ................................................................................... 35 1.6 block diagram ................................................................................................................... 36 1.7 functional outline ............................................................................................................ 39 chapter 2 pin functions .......................................................................................................... 41 2.1 pin function list ............................................................................................................... 41 2.2 description of pin functions .......................................................................................... 44 2.2.1 p00 to p07 (port 0) ................................................................................................................ 44 2.2.2 p10 to p17 (port 1) ................................................................................................................ 44 2.2.3 p20 to p27 (port 2) ................................................................................................................ 44 2.2.4 p30 to p37 (port 3) ................................................................................................................ 45 2.2.5 p40 to p47 (port 4) ................................................................................................................ 45 2.2.6 p50 to p57 (port 5) ................................................................................................................ 46 2.2.7 p60 to p67 (port 6) ................................................................................................................ 46 2.2.8 p70 to p77 (port 7) ................................................................................................................ 46 2.2.9 p100 to p102 (port 10) ......................................................................................................... 46 2.2.10 p120 to p124 (port 12) ......................................................................................................... 47 2.2.11 p130 to p137 (port 13) ......................................................................................................... 47 2.2.12 eo0, eo1 ............................................................................................................................... 47 2.2.13 vcol, vcoh ......................................................................................................................... 47 2.2.14 reset ............................................................................................................................... ..... 47 2.2.15 x1, x2 ............................................................................................................................... ...... 48 2.2.16 regosc ............................................................................................................................... .48 2.2.17 regcpu ............................................................................................................................... .48 2.2.18 v dd ............................................................................................................................... ........... 48 2.2.19 gnd0 to gnd2 ...................................................................................................................... 48 2.2.20 v dd port ............................................................................................................................... .48 2.2.21 gndport ............................................................................................................................. 48 2.2.22 v dd pll ............................................................................................................................ ....... 48 2.2.23 gndpll ............................................................................................................................... .. 48 2.2.24 av dd ............................................................................................................................... ........ 48 2.2.25 av ss ............................................................................................................................... ......... 48 2.2.26 v pp ( pd178f098 only) ......................................................................................................... 48 2.2.27 ic (mask rom versions only) ............................................................................................... 49 2.3 pin i/o circuits and recommended connection of unused pins ............................. 50 13 user? manual u12790ej2v0ud chapter 3 cpu architecture ................................................................................................. 54 3.1 memory spaces ................................................................................................................. 54 3.1.1 internal program memory space ........................................................................................... 58 3.1.2 internal data memory space .................................................................................................. 59 3.1.3 special-function register (sfr) area .................................................................................... 59 3.1.4 data memory addressing ...................................................................................................... 60 3.2 processor registers ......................................................................................................... 63 3.2.1 control registers .................................................................................................................... 63 3.2.2 general-purpose registers ..................................................................................................... 68 3.2.3 special-function registers (sfr) ........................................................................................... 70 3.3 instruction address addressing .................................................................................... 75 3.3.1 relative addressing ............................................................................................................... 75 3.3.2 immediate addressing ........................................................................................................... 76 3.3.3 table indirect addressing ...................................................................................................... 77 3.3.4 register addressing ............................................................................................................... 78 3.4 operand address addressing ........................................................................................ 79 3.4.1 implied addressing ................................................................................................................. 79 3.4.2 register addressing ............................................................................................................... 80 3.4.3 direct addressing ................................................................................................................... 81 3.4.4 short direct addressing ......................................................................................................... 82 3.4.5 special-function register (sfr) addressing .......................................................................... 83 3.4.6 register indirect addressing .................................................................................................. 84 3.4.7 based addressing .................................................................................................................. 85 3.4.8 based indexed addressing .................................................................................................... 86 3.4.9 stack addressing ................................................................................................................... 87 chapter 4 port functions ...................................................................................................... 88 4.1 port functions ................................................................................................................... 88 4.2 port configuration ............................................................................................................ 91 4.2.1 port 0 ............................................................................................................................... ....... 91 4.2.2 port 1 ............................................................................................................................... ....... 92 4.2.3 port 2 ............................................................................................................................... ....... 93 4.2.4 port 3 ............................................................................................................................... ....... 95 4.2.5 port 4 ............................................................................................................................... ....... 96 4.2.6 port 5 ............................................................................................................................... ....... 97 4.2.7 port 6 ............................................................................................................................... ....... 98 4.2.8 port 7 ............................................................................................................................... ....... 99 4.2.9 port 10 ............................................................................................................................... ..... 101 4.2.10 port 12 ............................................................................................................................... ..... 103 4.2.11 port 13 ............................................................................................................................... ..... 105 4.3 registers controlling port function .............................................................................. 106 4.4 port function operations ................................................................................................ 109 4.4.1 writing to i/o port .................................................................................................................. 109 4.4.2 reading from i/o port ............................................................................................................ 109 4.4.3 operations on i/o port ........................................................................................................... 109 14 user? manual u12790ej2v0ud chapter 5 clock generator ................................................................................................. 110 5.1 clock generator functions ............................................................................................. 110 5.2 clock generator configuration ....................................................................................... 111 5.3 clock generator control registers ................................................................................ 112 5.4 system clock oscillator .................................................................................................. 114 5.4.1 system clock oscillator .......................................................................................................... 114 5.4.2 incorrect resonator connection ............................................................................................. 115 5.4.3 divider ............................................................................................................................... ..... 116 5.5 clock generator operations ........................................................................................... 117 5.6 changing system clock and cpu clock settings ....................................................... 118 5.6.1 time required for switchover between system clock and cpu clock ................................. 118 chapter 6 16-bit timer/event counter 0 ........................................................................... 119 6.1 functions of 16-bit timer/event counter 0 .................................................................. 119 6.2 configuration of 16-bit timer/event counter 0 ............................................................ 121 6.3 registers controlling 16-bit timer/event counter 0 ................................................... 124 6.4 operation of 16-bit timer/event counter 0 ................................................................... 130 6.4.1 operation as interval timer .................................................................................................... 130 6.4.2 operation as external event counter .................................................................................... 132 6.4.3 pulse width measurement ..................................................................................................... 134 6.4.4 square wave output operation .............................................................................................. 141 6.4.5 one-shot pulse output operation .......................................................................................... 142 6.4.6 ppg output operation ............................................................................................................ 147 6.5 program list ...................................................................................................................... 149 6.5.1 interval timer .......................................................................................................................... 150 6.5.2 pulse width measurement by free-running counter and one capture register .................... 151 6.5.3 two-pulse-width measurement by free-running counter ..................................................... 152 6.5.4 pulse width measurement by restart .................................................................................... 154 6.5.5 ppg output ............................................................................................................................. 15 5 6.6 notes on 16-bit timer/event counter 0 ......................................................................... 156 chapter 7 8-bit timer/event counters 50, 51 ................................................................... 161 7.1 functions of 8-bit timer/event counters 50, 51 .......................................................... 161 7.2 configuration of 8-bit timer/event counters 50, 51 ................................................... 163 7.3 registers controlling 8-bit timer/event counters 50, 51 ........................................... 165 7.4 operations of 8-bit timer/event counters 50, 51 ........................................................ 170 7.4.1 operation as interval timer (8-bit) ......................................................................................... 170 7.4.2 operation as external event counter .................................................................................... 174 7.4.3 square-wave output operation (8-bit resolution) .................................................................. 175 7.4.4 8-bit pwm output operation .................................................................................................. 176 7.4.5 operation as interval timer (16-bit) ....................................................................................... 179 7.5 program list ...................................................................................................................... 181 7.5.1 interval timer (8-bit) ............................................................................................................... 181 7.5.2 external event counter .......................................................................................................... 182 7.5.3 interval timer (16-bit) ............................................................................................................. 183 15 user? manual u12790ej2v0ud 7.6 notes on 8-bit timer/event counters 50, 51 ................................................................ 184 chapter 8 basic timer ............................................................................................................... 185 8.1 function of basic timer .................................................................................................. 185 8.2 configuration of basic timer .......................................................................................... 185 8.3 operation of basic timer ................................................................................................. 186 chapter 9 watchdog timer .................................................................................................... 187 9.1 watchdog timer functions ............................................................................................. 187 9.2 watchdog timer configuration ....................................................................................... 189 9.3 watchdog timer control registers ................................................................................ 189 9.4 watchdog timer operations ........................................................................................... 192 9.4.1 operation as watchdog timer ................................................................................................ 192 9.4.2 operation as interval timer .................................................................................................... 193 chapter 10 buzzer output controllers ......................................................................... 194 10.1 functions of buzzer output controllers ....................................................................... 194 10.2 configuration of buzzer output controllers ................................................................. 195 10.3 registers controlling buzzer output controllers ........................................................ 195 10.3.1 beep0 ............................................................................................................................... ..... 195 10.3.2 buz ............................................................................................................................... ......... 196 10.4 operation of buzzer output controllers ....................................................................... 197 chapter 11 a/d converter ...................................................................................................... 198 11.1 a/d converter functions ................................................................................................. 198 11.2 a/d converter configuration ........................................................................................... 198 11.3 registers controlling a/d converter ............................................................................. 201 11.4 a/d converter operations ............................................................................................... 205 11.4.1 basic operations of a/d converter ........................................................................................ 205 11.4.2 input voltage and conversion results .................................................................................... 207 11.4.3 a/d converter operating modes ............................................................................................ 208 11.5 a/d converter cautions ................................................................................................... 214 chapter 12 overview of serial interface ...................................................................... 217 chapter 13 serial interface sio0 ........................................................................................ 218 13.1 functions of serial interface sio0 ................................................................................. 218 13.2 configuration of serial interface sio0 ........................................................................... 221 13.3 control registers of serial interface sio0 .................................................................... 226 13.4 operations of serial interface sio0 ............................................................................... 234 13.4.1 operation stop mode ............................................................................................................. 234 13.4.2 3-wire serial i/o mode operation ........................................................................................... 235 13.4.3 sbi mode operation ............................................................................................................... 239 16 user? manual u12790ej2v0ud 13.4.4 2-wire serial i/o mode operation ........................................................................................... 265 13.4.5 i 2 c bus mode operation ......................................................................................................... 270 13.4.6 cautions on use of i 2 c bus mode ......................................................................................... 290 13.4.7 restrictions in using i 2 c bus mode ....................................................................................... 292 13.4.8 sck0/scl/p27 pin output manipulation ............................................................................... 294 chapter 14 serial interface sio1 ........................................................................................ 295 14.1 functions of serial interface sio1 ................................................................................. 295 14.2 configuration of serial interface sio1 ........................................................................... 296 14.3 control registers of serial interface sio1 .................................................................... 299 14.4 operations of serial interface sio1 ............................................................................... 306 14.4.1 operation stop mode ............................................................................................................. 306 14.4.2 3-wire serial i/o mode operation ........................................................................................... 307 14.4.3 3-wire serial i/o mode operation with automatic transmit/receive function ........................ 311 chapter 15 serial interface sio3 ........................................................................................ 339 15.1 function of serial interface sio3 ................................................................................... 339 15.2 configuration of serial interface sio3 ........................................................................... 340 15.3 registers controlling serial interface sio3 .................................................................. 341 15.4 operation of serial interface sio3 ................................................................................. 343 15.4.1 operation stop mode ............................................................................................................. 343 15.4.2 3-wire serial i/o mode ........................................................................................................... 344 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) ......... 347 16.1 functions of serial interface uart0 ............................................................................. 347 16.2 configuration of serial interface uart0 ....................................................................... 349 16.3 registers controlling serial interface uart0 .............................................................. 351 16.4 operation of serial interface uart0 .............................................................................. 355 16.4.1 operation stop mode ............................................................................................................. 355 16.4.2 asynchronous serial interface (uart) mode ....................................................................... 356 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) ..................... 367 17.1 iebus controller functions ............................................................................................. 367 17.1.1 communication protocol of iebus ......................................................................................... 367 17.1.2 determination of bus mastership (arbitration) ...................................................................... 368 17.1.3 communication mode ............................................................................................................ 368 17.1.4 communication address ........................................................................................................ 368 17.1.5 broadcast communication ..................................................................................................... 369 17.1.6 transfer format of iebus ....................................................................................................... 369 17.1.7 transfer data .......................................................................................................................... 379 17.1.8 bit format ............................................................................................................................... . 382 17.2 simple iebus controller .................................................................................................. 383 17.3 iebus controller configuration ...................................................................................... 384 17.4 internal registers of iebus controller .......................................................................... 386 17 user? manual u12790ej2v0ud 17.4.1 internal register list ................................................................................................................ 386 17.4.2 description of internal registers ............................................................................................ 387 17.5 interrupt operations of iebus controller ...................................................................... 406 17.5.1 interrupt control block ............................................................................................................ 406 17.5.2 interrupt source list ................................................................................................................ 407 17.5.3 communication error source processing list ........................................................................ 408 17.6 interrupt generation timing and main cpu processing ............................................. 411 17.6.1 master transmission ............................................................................................................... 411 17.6.2 master reception .................................................................................................................... 413 17.6.3 slave transmission ................................................................................................................. 415 17.6.4 slave reception ...................................................................................................................... 417 17.6.5 interval of occurrence of interrupt for iebus control ............................................................ 419 chapter 18 interrupt functions ......................................................................................... 423 18.1 interrupt function types ................................................................................................. 423 18.2 interrupt sources and configuration ............................................................................. 423 18.3 interrupt function control registers ............................................................................. 432 18.4 interrupt servicing operations ....................................................................................... 438 18.4.1 non-maskable interrupt request acknowledgment operation .............................................. 438 18.4.2 maskable interrupt request acknowledgment operation ...................................................... 441 18.4.3 software interrupt request acknowledgment operation ....................................................... 444 18.4.4 multiple servicing interrupt .................................................................................................... 445 18.4.5 pending interrupt requests .................................................................................................... 448 chapter 19 pll frequency synthesizer ........................................................................... 449 19.1 function of pll frequency synthesizer ....................................................................... 449 19.2 configuration of pll frequency synthesizer .............................................................. 451 19.3 registers controlling pll frequency synthesizer ..................................................... 453 19.4 operation of pll frequency synthesizer ..................................................................... 457 19.4.1 operation of each block of pll frequency synthesizer ....................................................... 457 19.4.2 operation to set n value of pll frequency synthesizer ...................................................... 461 19.5 pll disable status ........................................................................................................... 466 19.6 notes on pll frequency synthesizer ........................................................................... 466 chapter 20 frequency counter ........................................................................................... 467 20.1 function of frequency counter ...................................................................................... 467 20.2 configuration of frequency counter ............................................................................. 467 20.3 registers controlling frequency counter .................................................................... 469 20.4 operation of frequency counter .................................................................................... 471 20.5 notes on frequency counter .......................................................................................... 473 chapter 21 standby function .............................................................................................. 475 21.1 standby function and configuration ............................................................................. 475 21.1.1 standby function .................................................................................................................... 475 18 user? manual u12790ej2v0ud 21.1.2 standby function control register .......................................................................................... 476 21.2 standby function operations ......................................................................................... 477 21.2.1 halt mode ............................................................................................................................ 477 21.2.2 stop mode ........................................................................................................................... 480 chapter 22 reset function .................................................................................................... 483 22.1 reset function .................................................................................................................. 483 22.2 power failure detection function .................................................................................. 491 22.3 4.5 v voltage detection function ................................................................................... 492 chapter 23 pd178f098 ............................................................................................................... 493 23.1 memory size select register .......................................................................................... 494 23.2 internal expansion ram size select register .............................................................. 495 23.3 flash memory features ................................................................................................... 496 23.3.1 programming environment .................................................................................................... 496 23.3.2 communication mode ............................................................................................................ 497 23.3.3 on-board pin handling ........................................................................................................... 500 23.3.4 connection of adapter for flash writing ................................................................................. 503 chapter 24 instruction set ................................................................................................... 505 24.1 conventions ....................................................................................................................... 506 24.1.1 operand identifiers and description method ........................................................................ 506 24.1.2 description of ?peration?column ......................................................................................... 507 24.1.3 description of ?lag operation?column .................................................................................. 507 24.2 operation list .................................................................................................................... 508 24.3 instructions listed by addressing type ....................................................................... 516 chapter 25 electrical specifications .............................................................................. 520 chapter 26 package drawing ............................................................................................... 539 chapter 27 recommended soldering conditions ........................................................ 540 appendix a development tools ........................................................................................ 541 a.1 software package ............................................................................................................. 543 a.2 language processing software ...................................................................................... 543 a.3 control software ............................................................................................................... 544 a.4 flash memory writing tools ........................................................................................... 544 a.5 debugging tools (hardware) .......................................................................................... 545 a.5.1 when using in-circuit emulator ie-78k0-ns, ie-78k0-ns-a ............................................... 545 a.5.2 when using in-circuit emulator ie-78001-r-a ...................................................................... 546 a.6 debugging tools (software) ........................................................................................... 547 a.7 embedded software ......................................................................................................... 548 a.8 upgrading old version of in-circuit emulator for 78k/0 series to ie-78001-r-a ... 549 19 user? manual u12790ej2v0ud a.9 drawing for conversion socket (ev-9200gf-100) package and recommended board ............................................................................................................................... ... 550 appendix b register index ...................................................................................................... 552 b.1 register index (register name) ....................................................................................... 552 b.2 register index (symbol) .................................................................................................... 555 appendix c revision history ................................................................................................ .... 558 20 user? manual u12790ej2v0ud list of figures (1/8) figure no. title page 2-1 pin i/o circuits ............................................................................................................................... ..... 52 3-1 memory map ( pd178076, 178096a) ............................................................................................... 55 3-2 memory map ( pd178078, 178098a) ............................................................................................... 56 3-3 memory map ( pd178f098) .............................................................................................................. 57 3-4 correspondence between data memory and addressing ( pd178076, 178096a) ........................ 60 3-5 correspondence between data memory and addressing ( pd178078, 178098a) ........................ 61 3-6 correspondence between data memory and addressing ( pd178f098) ...................................... 62 3-7 configuration of program counter ..................................................................................................... 63 3-8 configuration of program status word .............................................................................................. 63 3-9 configuration of stack pointer ........................................................................................................... 65 3-10 data to be saved to stack memory ................................................................................................... 66 3-11 data to be restored from stack memory .......................................................................................... 67 3-12 general-purpose register configuration ........................................................................................... 69 4-1 port types ............................................................................................................................... ............ 88 4-2 block diagram of p00 to p07 ............................................................................................................. 91 4-3 block diagram of p10 to p17 ............................................................................................................. 92 4-4 block diagram of p20 to p26 ............................................................................................................. 93 4-5 block diagram of p27 ......................................................................................................................... 94 4-6 block diagram of p30 to p37 ............................................................................................................. 95 4-7 block diagram of p40 to p47 ............................................................................................................. 96 4-8 block diagram of p50 to p57 ............................................................................................................. 97 4-9 block diagram of p60 to p67 ............................................................................................................. 98 4-10 block diagram of p70 to p72, p74, and p75 .................................................................................... 99 4-11 block diagram of p73, p76, and p77 ................................................................................................ 100 4-12 block diagram of p100 ....................................................................................................................... 101 4-13 block diagram of p101 and p102 ...................................................................................................... 102 4-14 block diagram of p120 and p121 ...................................................................................................... 103 4-15 block diagram of p122 to p124 ......................................................................................................... 104 4-16 block diagram of p130 to p137 ......................................................................................................... 105 4-17 format of port mode registers .......................................................................................................... 108 5-1 format of dts system clock select register (dtsck) .................................................................. 110 5-2 block diagram of clock generator .................................................................................................... 111 5-3 format of processor clock control register ..................................................................................... 112 5-4 format of oscillation stabilization time select register (osts) .................................................... 113 5-5 external circuit of system clock oscillator ....................................................................................... 114 5-6 examples of incorrect connection resonator ................................................................................... 115 6-1 block diagram of 16-bit timer/event counter 0 ............................................................................... 120 6-2 format of 16-bit timer mode control register 0 (tmc0) ................................................................ 125 6-3 format of capture/compare control register 0 (crc0) .................................................................. 126 21 user? manual u12790ej2v0ud 6-4 format of 16-bit timer output control register 0 (toc0) ............................................................... 127 6-5 format of prescaler mode register 0 (prm0) .................................................................................. 128 6-6 format of port mode register 3 (pm3) ............................................................................................. 129 6-7 setting of control registers for interval timer operation ................................................................ 130 6-8 configuration of interval timer ........................................................................................................... 131 6-9 timing of interval timer operation .................................................................................................... 131 6-10 setting of control registers in external event counter mode ......................................................... 132 6-11 configuration of external event counter ........................................................................................... 133 6-12 timing of external event counter (with rising edge specified) ...................................................... 133 6-13 setting of control registers for pulse width measurement with free-running counter and one capture register ......................................................................................................................... 134 6-14 configuration of pulse width measurement circuit with free-running counter ............................ 135 6-15 timing of pulse width measurement with free-running counter and one capture register (with both rising and falling edges specified) ................................................................................ 135 6-16 setting of control registers for measurement of two pulse widths with free-running counter ............................................................................................................................... ................. 136 6-17 capture operation of cr01 when rising edge is specified ........................................................... 137 6-18 timing of pulse width measurement by free-running counter (with both rising and falling edges specified) ............................................................................................................................... .. 137 6-19 setting of control registers for measurement with free-running counter and two capture registers ............................................................................................................................... .............. 138 6-20 timing of pulse width measurement with free-running counter and two capture registers (with rising edge specified) .............................................................................................................. 139 6-21 setting of control registers for pulse measurement by restarting ................................................. 140 6-22 timing of pulse width measurement by restarting (with rising edge specified) .......................... 140 6-23 setting of control register in square wave output mode ............................................................... 141 6-24 timing of square wave output operation ........................................................................................ 142 6-25 setting of control registers for one-shot pulse output operation with software trigger ............ 143 6-26 timing of one-shot pulse output operation with software trigger ................................................ 144 6-27 setting of control registers for one-shot pulse output operation with external trigger ............. 145 6-28 timing of one-shot pulse output operation with external trigger (clear & start at valid edge of ti00 with rising edge specified) ................................................................................................... 146 6-29 setting of control register for ppg output operation ..................................................................... 147 6-30 configuration of ppg output ............................................................................................................. 148 6-31 ppg output operation timing ........................................................................................................... 148 6-32 start timing of 16-bit timer counter 0 .............................................................................................. 156 6-33 timing after changing value of compare register during timer count operation ....................... 156 6-34 data retention timing of capture register ...................................................................................... 157 6-35 operation timing of ovf0 flag ......................................................................................................... 158 6-36 cr01 capture operation with rising edge specified ....................................................................... 159 7-1 block diagram of 8-bit timer/event counter 50 ............................................................................... 162 7-2 block diagram of 8-bit timer/event counter 51 ............................................................................... 162 list of figures (2/8) figure no. title page 22 user? manual u12790ej2v0ud 7-3 format of timer clock select register 50 (tcl50) .......................................................................... 165 7-4 format of timer clock select register 51 (tcl51) .......................................................................... 166 7-5 format of 8-bit timer mode control register 50 (tmc50) .............................................................. 167 7-6 format of 8-bit timer mode control register 51 (tmc51) .............................................................. 168 7-7 format of port mode register 3 (pm3) ............................................................................................. 169 7-8 timing of interval timer operation .................................................................................................... 171 7-9 operation timing of external event counter (with rising edge specified) ..................................... 174 7-10 timing of square-wave output operation ........................................................................................ 175 7-11 operation timing of pwm output ...................................................................................................... 177 7-12 timing of operation when cr5n is changed ................................................................................... 178 7-13 16-bit cascade connection mode ..................................................................................................... 180 7-14 start timing of 8-bit timer counter 5n .............................................................................................. 184 8-1 block diagram of basic timer ............................................................................................................ 185 8-2 timing of basic timer operation ....................................................................................................... 186 8-3 operation timing to poll btmif0 flag .............................................................................................. 186 9-1 block diagram of watchdog timer .................................................................................................... 187 9-2 format of watchdog timer clock select register (wdcs) ............................................................. 190 9-3 format of watchdog timer mode register (wdtm) ........................................................................ 191 10-1 block diagram of beep0 .................................................................................................................... 194 10-2 block diagram of buz ........................................................................................................................ 194 10-3 format of beep frequency select register 0 (beepcl0) .............................................................. 196 10-4 format of clock output select register (cks) ................................................................................. 196 11-1 block diagram of a/d converter ........................................................................................................ 199 11-2 format of a/d converter mode register 3 (adm3) .......................................................................... 202 11-3 format of analog input channel specification register 3 (ads3) .................................................. 203 11-4 format of power-fail comparison mode register 3 (pfm3) ........................................................... 204 11-5 basic operation of a/d converter ...................................................................................................... 206 11-6 relationship between analog input voltage and a/d conversion result ....................................... 207 11-7 a/d conversion operation .................................................................................................................. 209 11-8 power-fail comparison threshold value register 3 (pft3) ........................................................... 210 11-9 a/d conversion operation in power-fail comparison mode ........................................................... 211 11-10 circuit configuration of series resistor string .................................................................................. 214 11-11 analog input pin handling .................................................................................................................. 215 11-12 a/d conversion end interrupt request generation timing .............................................................. 216 13-1 system configuration example of serial bus interface (sbi) .......................................................... 219 13-2 serial bus configuration example using i 2 c bus ............................................................................. 220 13-3 block diagram of serial interface sio0 ............................................................................................. 222 13-4 format of serial interface clock select register 0 (scl0) .............................................................. 226 list of figures (3/8) figure no. title page 23 user? manual u12790ej2v0ud 13-5 format of serial operating mode register 0 (csim0) ...................................................................... 227 13-6 format of serial bus interface control register 0 (sbic0) .............................................................. 229 13-7 format of interrupt timing specification register 0 (sint0) ........................................................... 232 13-8 3-wire serial i/o mode timing ........................................................................................................... 237 13-9 relt and cmdt operations ............................................................................................................. 237 13-10 circuit for switching transfer bit order ............................................................................................. 238 13-11 example of serial bus configuration with sbi .................................................................................. 239 13-12 sbi transfer timing ............................................................................................................................ 241 13-13 bus release signal ............................................................................................................................ 242 13-14 command signal ............................................................................................................................... .. 242 13-15 addresses ............................................................................................................................... ............. 243 13-16 slave selection by address ................................................................................................................ 243 13-17 commands ............................................................................................................................... ........... 244 13-18 data ............................................................................................................................... ...................... 244 13-19 acknowledge signal ............................................................................................................................ 245 13-20 busy and ready signals ................................................................................................................. 246 13-21 relt, cmdt, reld, and cmdd operations (master) .................................................................... 251 13-22 reld and cmdd operations (slave) ................................................................................................ 251 13-23 ackt operation ............................................................................................................................... ... 252 13-24 acke operations ............................................................................................................................... . 253 13-25 ackd operations ............................................................................................................................... . 254 13-26 bsye operation ............................................................................................................................... ... 254 13-27 pin configuration ............................................................................................................................... . 257 13-28 address transmission from master device to slave device (wup = 1) ......................................... 259 13-29 command transmission from master device to slave device ........................................................ 260 13-30 data transmission from master device to slave device ................................................................. 261 13-31 data transmission from slave device to master device ................................................................. 262 13-32 serial bus configuration example using 2-wire serial i/o mode .................................................... 265 13-33 2-wire serial i/o mode timing ........................................................................................................... 268 13-34 relt and cmdt operations ............................................................................................................. 269 13-35 serial bus configuration example using i 2 c bus ............................................................................. 270 13-36 i 2 c bus serial data transfer timing .................................................................................................. 271 13-37 start condition ............................................................................................................................... ..... 272 13-38 address ............................................................................................................................... ................ 272 13-39 transfer direction specification ......................................................................................................... 272 13-40 acknowledge signal ............................................................................................................................ 273 13-41 stop condition ............................................................................................................................... ...... 273 13-42 wait signal ............................................................................................................................... ........... 274 13-43 pin configuration ............................................................................................................................... . 281 13-44 data transmission from master to slave (both master and slave selected 9-clock wait) ........... 283 13-45 data transmission from slave to master (both master and slave selected 9-clock wait) ........... 286 13-46 start condition output ........................................................................................................................ 290 13-47 slave wait release (transmission) ................................................................................................... 291 list of figures (4/8) figure no. title page 24 user? manual u12790ej2v0ud 13-48 sck0/scl/p27 pin configuration ...................................................................................................... 294 14-1 block diagram of serial interface sio1 ............................................................................................. 297 14-2 format of serial operating mode register 1 (csim1) ...................................................................... 300 14-3 format of automatic data transmit/receive control register (adtc) ........................................... 301 14-4 format of automatic data transmit/receive interval specification register (adti) ...................... 303 14-5 format of port mode register 2 (pm2) ............................................................................................. 305 14-6 3-wire serial i/o mode timing ........................................................................................................... 309 14-7 circuit for switching transfer bit order ............................................................................................. 310 14-8 basic transmit/receive mode operation timing .............................................................................. 319 14-9 basic transmit/receive mode flowchart .......................................................................................... 320 14-10 buffer ram operation in 6-byte transmission/reception (in basic transmit/receive mode) ..... 321 14-11 basic transmit mode operation timing ............................................................................................ 323 14-12 basic transmit mode flowchart ......................................................................................................... 324 14-13 buffer ram operation in 6-byte transmission (in basic transmit mode) ....................................... 325 14-14 repeat transmit mode operation timing .......................................................................................... 327 14-15 repeat transmit mode flowchart ...................................................................................................... 328 14-16 buffer ram operation in 6-byte transmission (in repeat transmit mode) .................................... 329 14-17 automatic transmission/reception suspension and restart ........................................................... 331 14-18 system configuration when busy control option is used .............................................................. 332 14-19 operation timing when busy control option is used (when busy0 = 0) .................................... 333 14-20 busy signal and wait release (when busy0 = 0) .......................................................................... 334 14-21 operation timing when strobe control option is used ................................................................... 334 14-22 operation timing when busy & strobe control option is used (when busy0 = 0) ..................... 336 14-23 operation timing of bit shift detection function by busy signal (when busy0 = 1) ................... 337 14-24 interval time of automatic transmission/reception ......................................................................... 338 15-1 block diagram of serial interface sio3 ............................................................................................. 339 15-2 format of serial operating mode register 3 (csim3) ...................................................................... 341 15-3 format of port mode register 7 (pm7) ............................................................................................. 342 15-4 timing in 3-wire serial i/o mode ....................................................................................................... 346 16-1 block diagram of serial interface uart0 ......................................................................................... 347 16-2 block diagram of baud rate generator ............................................................................................ 348 16-3 format of asynchronous serial interface mode register 0 (asim0) ............................................... 352 16-4 format of asynchronous serial interface register 0 (asis0) .......................................................... 353 16-5 format of baud rate generator control register 0 (brgc0) ......................................................... 354 16-6 permissible error of baud rate allowing for sampling error (k = 0) ............................................... 361 16-7 format of transmit/receive data of asynchronous serial interface ............................................... 362 16-8 generation timing of transmission completion interrupt request of asynchronous serial interface ...................................................................................................................... ......................... 364 16-9 timing of generation of reception completion interrupt of asynchronous serial interface .......... 365 16-10 reception error timing ....................................................................................................................... 366 list of figures (5/8) figure no. title page 25 user? manual u12790ej2v0ud 17-1 iebus transfer signal format ............................................................................................................ 369 17-2 master address field .......................................................................................................................... 370 17-3 slave address field ............................................................................................................................ 371 17-4 control field ............................................................................................................................... ......... 373 17-5 telegraph length field ....................................................................................................................... 375 17-6 data field ............................................................................................................................... ............. 376 17-7 bit configuration of slave status ....................................................................................................... 380 17-8 configuration of lock address ........................................................................................................... 381 17-9 bit format of iebus ............................................................................................................................. 38 2 17-10 iebus controller block diagram ......................................................................................................... 384 17-11 format of iebus control register 0 (bcr0) ..................................................................................... 387 17-12 format of iebus unit address register (uar) ................................................................................. 390 17-13 format of iebus slave address register (sar) ............................................................................... 390 17-14 format of iebus partner address register (par) ............................................................................ 390 17-15 format of iebus control data register (cdr) ................................................................................. 391 17-16 interrupt generation timing (for (1), (3), and (4)) ............................................................................. 392 17-17 interrupt generation timing (for (2) and (5)) ..................................................................................... 392 17-18 timing of intie2 interrupt generation in locked state (for (4) and (5)) ......................................... 393 17-19 timing of intie2 interrupt generation in locked state (for (3)) ...................................................... 393 17-20 format of iebus telegraph length register (dlr) .......................................................................... 394 17-21 format of iebus data register (dr) ................................................................................................. 395 17-22 format of iebus unit status register (usr) .................................................................................... 396 17-23 example of broadcast communication flag operation .................................................................... 397 17-24 format of iebus interrupt status register (isr) ............................................................................... 400 17-25 format of iebus slave status register (ssr) .................................................................................. 404 17-26 format of iebus communication success counter (scr) .............................................................. 405 17-27 format of iebus transmit counter (ccr) ......................................................................................... 405 17-28 configuration of interrupt control block ............................................................................................ 406 17-29 master transmission ........................................................................................................................... 411 17-30 master reception ............................................................................................................................... . 413 17-31 slave transmission ............................................................................................................................. 41 5 17-32 slave reception ............................................................................................................................... ... 417 17-33 master transmission (interval of interrupt occurrence) ................................................................... 419 17-34 master reception (interval of interrupt occurrence) ......................................................................... 420 17-35 slave transmission (interval of interrupt occurrence) ..................................................................... 421 17-36 slave reception (interval of interrupt occurrence) ........................................................................... 422 18-1 basic configuration of interrupt function .......................................................................................... 430 18-2 format of interrupt request flag registers (if0l, if0h, if1l) ....................................................... 433 18-3 format of interrupt mask flag registers (mk0l, mk0h, mk1l) ..................................................... 434 18-4 format of priority specification flag registes (pr0l, pr0h, pr1l) .............................................. 435 18-5 format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) ................................................................................................. 436 list of figures (6/8) figure no. title page 26 user? manual u12790ej2v0ud 18-6 configuration of program status word .............................................................................................. 437 18-7 flowchart from generation of non-maskable interrupt request to acknowledgment .................... 439 18-8 non-maskable interrupt request acknowledgment timing .............................................................. 439 18-9 non-maskable interrupt request acknowledgment operation ......................................................... 440 18-10 interrupt request acknowledgment processing algorithm ............................................................... 442 18-11 interrupt request acknowledgment timing (minimum time) ........................................................... 443 18-12 interrupt request acknowledgment timing (maximum time) .......................................................... 443 18-13 example of multiple interrupt servicing ............................................................................................. 446 18-14 pending interrupt requests ................................................................................................................ 448 19-1 block diagram of pll frequency synthesizer .................................................................................. 451 19-2 format of pll mode select register (pllmd) ................................................................................. 453 19-3 format of pll reference mode register (pllrf) ........................................................................... 454 19-4 format of pll unlock ff judge register (pllul) .......................................................................... 455 19-5 format of pll data transfer register (pllns) ............................................................................... 456 19-6 configuration of input select block and programmable divider ...................................................... 457 19-7 reference frequency generator configuration ................................................................................ 458 19-8 phase comparator, charge pump, and unlock ff configuration ................................................... 458 19-9 relationship between f r , f n , up, and dw .......................................................................................... 459 19-10 error out pin configuration ................................................................................................................ 460 20-1 frequency counter block diagram .................................................................................................... 468 20-2 format of if counter mode select register (ifcmd) ...................................................................... 469 20-3 format of if counter control register (ifccr) ............................................................................... 470 20-4 format of if counter gate judge register (ifcjg) ......................................................................... 470 20-5 block diagram of input pin and mode selection ............................................................................... 471 20-6 gate timing of frequency counter .................................................................................................... 472 20-7 frequency counter input pin circuit .................................................................................................. 473 20-8 gate status when halt instruction is executed ............................................................................. 473 21-1 format of oscillation stabilization time select register (osts) .................................................... 476 21-2 halt mode release upon interrupt generation ............................................................................... 478 21-3 halt mode release by reset input ............................................................................................... 479 21-4 stop mode release by interrupt request generation .................................................................... 481 21-5 release by stop mode reset input .............................................................................................. 482 22-1 reset function block diagram ........................................................................................................... 484 22-2 timing of reset by reset input ....................................................................................................... 485 22-3 timing of reset due to watchdog timer overflow ........................................................................... 486 22-4 timing of reset by power-on clear ................................................................................................... 487 22-5 format of poc status register (pocs) ........................................................................................... 491 22-6 format of poc status register (pocs) ........................................................................................... 492 22-7 format of vm45 control register (vm45c) ...................................................................................... 492 list of figures (7/8) figure no. title page 27 user? manual u12790ej2v0ud 23-1 format of memory size select register (ims) .................................................................................. 494 23-2 format of internal expansion ram size select register (ixs) ....................................................... 495 23-3 environment for writing program to flash memory .......................................................................... 496 23-4 communication mode selection format ............................................................................................ 497 23-5 example of connection with dedicated flash programmer ............................................................. 498 23-6 v pp pin connection example ............................................................................................................. 500 23-7 signal conflict (input pin of serial interface) .................................................................................... 501 23-8 abnormal operation of other device ................................................................................................. 501 23-9 signal conflict (reset pin) ............................................................................................................... 502 23-10 wiring example for flash writing adapter in 3-wire serial i/o mode ............................................. 503 23-11 wiring example for flash writing adapter in uart ......................................................................... 504 a-1 configuration of development tools .................................................................................................. 542 a-2 ev-9200gf-100 package drawing (for reference only) ................................................................. 550 a-3 ev-9200gf-100 recommended board mounting pattern (for reference only) ............................. 551 list of figures (8/8) figure no. title page 28 user? manual u12790ej2v0ud list of tables (1/3) table no. title page 2-1 pin i/o circuit types ........................................................................................................................... 50 3-1 internal memory capacity ................................................................................................................... 58 3-2 vector table ............................................................................................................................... ......... 58 3-3 absolute addresses of general-purpose registers .......................................................................... 68 3-4 special-function registers ................................................................................................................. 71 4-1 port functions ............................................................................................................................... ...... 89 4-2 configuration of port ........................................................................................................................... 91 4-3 port mode register and output latch settings when using alternate functions .......................... 107 5-1 configuration of clock generator ...................................................................................................... 111 5-2 maximum time required for cpu clock switchover ....................................................................... 118 6-1 configuration of 16-bit timer/event counter 0 ................................................................................. 121 6-2 cr00 capture trigger and valid edges of ti00 and ti01 pins ....................................................... 122 6-3 cr01 capture trigger and valid edge of ti00 pin (crc02 = 1) .................................................... 123 7-1 configuration of 8-bit timer/event counters 50 and 51 ................................................................... 163 9-1 watchdog timer inadvertent program loop detection time ........................................................... 188 9-2 interval time ............................................................................................................................... ........ 188 9-3 configuration of watchdog timer ...................................................................................................... 189 9-4 watchdog timer inadvertent program loop detection time ........................................................... 192 9-5 interval timer interval time ............................................................................................................... 193 10-1 configuration of buzzer output controllers ....................................................................................... 195 11-1 configuration of a/d converter .......................................................................................................... 198 12-1 differences between pd178096a and 178098a, and pd178076, 178078, and 178f098 ......... 217 13-1 configuration of serial interface sio0 ............................................................................................... 221 13-2 serial interface sio0 interrupt request signal generation .............................................................. 225 13-3 signals in sbi mode ........................................................................................................................... 255 13-4 signals in i 2 c bus mode ..................................................................................................................... 280 14-1 configuration of serial interface sio1 ............................................................................................... 296 14-2 timing of interrupt request signal generation ................................................................................. 338 15-1 configuration of serial interface sio3 ............................................................................................... 340 16-1 configuration of serial interface uart0 ........................................................................................... 349 29 user? manual u12790ej2v0ud 16-2 brgc0 set value for each baud rate ............................................................................................. 360 16-3 causes of reception errors ............................................................................................................... 366 17-1 transfer rate and maximum number of transfer bytes in communication mode 1 ...................... 368 17-2 contents of control bits ..................................................................................................................... 372 17-3 control field for locked slave unit ................................................................................................... 373 17-4 control field for unlocked slave unit ................................................................................................ 373 17-5 acknowledge signal output conditions of control field .................................................................. 374 17-6 contents of telegraph length bit ...................................................................................................... 375 17-7 comparison of existing and simple iebus interface functions ....................................................... 383 17-8 internal registers of iebus controller ............................................................................................... 386 17-9 reset conditions of flags in isr register ........................................................................................ 399 17-10 interrupt source list ........................................................................................................................... 407 17-11 communication error source processing list ................................................................................... 408 18-1 interrupt sources ............................................................................................................................... . 424 18-2 flags corresponding to interrupt request sources .......................................................................... 432 18-3 times from maskable interrupt request generation to interrupt servicing .................................... 441 18-4 interrupt requests enabled for multiple interrupt servicing ............................................................. 445 19-1 division mode, input pin, and division value .................................................................................... 450 19-2 configuration of pll frequency synthesizer .................................................................................... 451 19-3 error out output signal ...................................................................................................................... 460 19-4 operation of each block and register status in pll disable status .............................................. 466 20-1 configuration of frequency counter .................................................................................................. 467 21-1 halt mode operating status ............................................................................................................ 477 21-2 operation after halt mode release ................................................................................................ 479 21-3 stop mode operating status ............................................................................................................ 480 21-4 operation after stop mode release ............................................................................................... 482 22-1 hardware status after reset .............................................................................................................. 488 23-1 differences between pd178f098 and mask rom versions ......................................................... 493 23-2 set value of memory size select register ....................................................................................... 494 23-3 set value of internal expansion ram size select register ............................................................. 495 23-4 communication mode list .................................................................................................................. 497 23-5 pin connection list ............................................................................................................................. 49 9 24-1 operand symbols and descriptions .................................................................................................. 506 list of tables (2/3) table no. title page 30 user? manual u12790ej2v0ud 27-1 soldering conditions for surface-mount type .................................................................................. 540 a-1 upgrading old version of in-circuit emulator for 78k/0 series to ie-78001-r-a ........................... 549 list of tables (3/3) table no. title page 31 user? manual u12790ej2v0ud chapter 1 outline 1.1 features on-chip high-capacity rom and ram instruction set suitable for system control bit processing across entire address space multiplication/division instructions general-purpose i/o ports: 80 pins iebus tm controller ( pd178096a, 178098a, and 178f098 only) hardware for pll frequency synthesizer dual modulus prescaler (160 mhz max.) programmable divider phase comparator charge pump frequency counter 8-bit resolution a/d converter: 8 channels serial interface: 4-channel clocked 3-wire serial i/o/sbi/2-wire serial i/o/i 2 c bus note mode selectable: 1 channel 3-wire serial i/o mode: 1 channel 3-wire serial i/o mode (with automatic transfer/receive function): 1 channel uart mode: 1 channel ( pd178076, 178078, and 178f098 only) note when using the i 2 c bus mode (including when this mode is implemented by software without using the internal hardware), consult nec electronics when placing a mask order. program memory (rom) data memory part number type 48 kb 60 kb 48 kb 60 kb 60 kb (flash memory) 1024 bytes internal high-speed ram buffer ram internal expansion ram 32 bytes 1024 bytes 2048 bytes 1024 bytes 2048 bytes pd178076 pd178078 pd178096a pd178098a pd178f098 32 chapter 1 outline user? manual u12790ej2v0ud timer: 5 channels basic timer (timer carry ff): 1 channel 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watchdog timer: 1 channel vectored interrupts pd178076, 178078: 22 sources pd178096a, 178098a: 21 sources pd178f098: 24 sources item non-maskable maskable interrupt software interrupt part number interrupt external internal pd178076 1 source note 8 sources 13 sources note 1 source pd178078 pd178096a 12 sources note pd178098a pd178f098 15 sources note note either a non-maskable interrupt or maskable interrupt (internal) can be selected as the interrupt source of the watchdog timer (intwdt). test input: 1 pin instruction cycle: 0.317/0.635/1.27/2.54/5.08 s (with 6.3 mhz crystal resonator) 0.444/0.889/1.778/3.556/7.111 s (with 4.5 mhz crystal resonator) supply voltage: v dd = 4.5 to 5.5 v (with pll, cpu operating) v dd = 3.5 to 5.5 v (with cpu operating) power-on clear circuit 1.2 applications car stereo 1.3 ordering information part number package internal rom pd178076gf- -3ba 100-pin plastic qfp (14 20 mm, 0.65-mm pitch) mask rom pd178078gf- -3ba 100-pin plastic qfp (14 20 mm, 0.65-mm pitch) mask rom pd178096agf- -3ba 100-pin plastic qfp (14 20 mm, 0.65-mm pitch) mask rom pd178098agf- -3ba 100-pin plastic qfp (14 20 mm, 0.65-mm pitch) mask rom pd178f098gf-3ba 100-pin plastic qfp (14 20 mm, 0.65-mm pitch) flash memory remark indicates rom code suffix. when using i 2 c bus mode, e is the rom code suffix. 33 chapter 1 outline user? manual u12790ej2v0ud 1.4 pin configuration (top view) 100-pin plastic qfp (14 20 mm, 0.65 mm pitch) pd178076gf- -3ba, 178078gf- -3ba pd178096agf- -3ba, 178098agf- -3ba pd178f098gf-3ba 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 p06/intp6 p05/intp5 p04/intp4 p124 p123 p122 p121 /rx0 p120 /tx0 p77 p76 p75[/txd0] p74[/rxd0] p137 p136 p135 p134 p133 p132 p131/to51 p130/to50 p37/buz p36/beep0 p35/ti51 p34/ti50 p33/ti01 p32/ti00 p31/to0 p30/vm45 p03/intp3 p02/intp2 p00/intp0 p01/intp1 p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0/sda0 p26/so0/sb1/sda1 p27/sck0/scl p70/si3 p71/so3 p72/sck3 p73 p50 p51 p52 p53 p54 p55 p56 p57 p10/ani0 p11/ani1 p12/ani2 p13/ani3 av dd p14/ani4 p15/ani5 p16/ani6 gndport v dd port p47 p46 p45 p44 p43 p42 p41 p40 p67 p66 p65 p64 p63 p62 p61 p60 gnd1 p07/intp7 p17/ani7 av ss regcpu v dd regosc x2 x1 gnd0 p100 gnd2 p101/amifc p102/fmifc v dd pll vcoh vcol gndpll eo0 eo1 ic (v pp ) reset 34 chapter 1 outline user s manual u12790ej2v0ud cautions 1. directly connect the ic (internally connected) pin to gnd0, gnd1, or gnd2. 2. keep the voltage at the av dd , v dd port, and v dd pll pins the same as that at the v dd pin. 3. keep the voltage at the av ss , gndport, and gndpll pins the same as that at gnd0, gnd1, or gnd2. 4. connect each of the regosc and regcpu pins to gnd via a 0.1 f capacitor. remark ( ) : pd178f098 only [ ] : pd178076 and 178078 only { } : pd178096a and 178098a only pin name amifc: am intermediate frequency counter input ani0 to ani7: a/d converter input av dd : a/d converter power supply av ss : a/d converter ground busy: busy input beep0, buz: buzzer output eo0, eo1: error out output fmifc: fm intermediate frequency counter input gndpll: pll ground gndport: port ground gnd0 to gnd2: ground ic: internally connected intp0 to intp7: interrupt input p00 to p07: port 0 p10 to p17: port 1 p20 to p27: port 2 p30 to p37: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p67: port 6 p70 to p77: port 7 p100 to p102: port 10 p120 to p124: port 12 p130 to p137: port 13 regcpu: regulator for cpu power supply regosc: regulator for oscillator reset: reset input rxd0 note 1 : uart0 serial data input rx0 note 2 : iebus serial data input sb0, sb1: serial data bus input/output sck0, sck1, sck3: serial clock input/output scl: serial clock input/output sda0, sda1: serial data input/output si0, si1, si3: serial data input so0, so1, so3: serial data output stb: strobe output ti00, ti01: 16-bit timer capture trigger input ti50, ti51: 8-bit timer clock input to0: 16-bit timer output to50, to51: 8-bit timer output txd0 note 1 : uart0 serial data output tx0 note 2 : iebus serial data output vcol, vcoh: local oscillation input v dd port: port power supply v dd pll: pll power supply v dd : power supply vm45: v dd = 4.5 v monitor output v pp note 3 : programming power supply x1, x2: crystal resonator notes 1. pd178076, 178078, and 178f098 only 2. pd178096a, 178098a, and 178f098 only 3. pd178f098 only 35 chapter 1 outline user s manual u12790ej2v0ud 1.5 development of 8-bit dts series products under mass production es products (for development evaluation) only 100 pins 100 pins 100 pins on-chip iebus controller on-chip iebus controller and uart on-chip uart pd178098a subseries pd178078 subseries pd178048 subseries 80 pins 80 pins on-chip osd controller 8-bit pwm 4 channels 14-bit pwm 1 channel pd178f048 pd178f098 pd178f054 pd178f124 pd178p018a 80 pins 80 pins timer and 3-wire serial i/o enhanced timer and 3-wire serial i/o enhanced pd178054 subseries on-chip osd controller 8-bit pwm 4 channels 14-bit pwm 1 channel 80 pins 80 pins on-chip uart on-chip uart pd178054 subseries 80 pins 80 pins 80 pins limits functions of pd178018a subseries pd178018a subseries pd178003 subseries flash memory product or prom product mask rom product 36 chapter 1 outline user s manual u12790ej2v0ud 1.6 block diagram (1) pd178076, 178078 16-bit timer/ event counter 8-bit timer/ event counter 50 8-bit timer/ event counter 51 watchdog timer basic timer serial interface 0 serial interface 1 uart0 interrupt control buzzer output system control 78k/0 cpu core rom pd178078 : 60 kb pd178076 : 48 kb 8 8 8 8 8 8 8 8 8 3 5 8 8 p00 to p07 a/d converter ani0/p10 to ani7/p17 frequency counter pll voltage regulator pll voltage regulator ti00/p32 ti01/p33 to0/p31 ti50/p34 to50/p130 ti51/p35 to51/p131 si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 serial interface 3 si3/p70 so3/p71 sck3/p72 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 reset x1 x2 v dd port gndport v dd reset cpu peripheral vm45/p30 regosc regcpu gnd0 v osc v cpu rxd0/p74 txd0/p75 intp0/p00 to intp7/p07 beep0/p36 buz/p37 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 10 port 12 port 13 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p77 p100 to p102 p120 to p124 p130 to p137 amifc/p101 fmifc/p102 eo0 eo1 vcol vcoh v dd pll gndpll av dd av ss ic gnd2 gnd1 ram pd178078 : 3 kb pd178076 : 2 kb 37 chapter 1 outline user s manual u12790ej2v0ud (2) pd178096a, 178098a 16-bit timer/ event counter 8-bit timer/ event counter 50 8-bit timer/ event counter 51 watchdog timer basic timer serial interface 0 serial interface 1 iebus 0 interrupt control buzzer output system control 8 8 8 8 8 8 8 8 8 3 5 8 8 p00 to p07 a/d converter ani0/p10 to ani7/p17 frequency counter pll voltage regulator pll voltage regulator ti00/p32 ti01/p33 to0/p31 ti50/p34 to50/p130 ti51/p35 to51/p131 si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 serial interface 3 si3/p70 so3/p71 sck3/p72 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 reset x1 x2 v dd port gndport v dd reset cpu peripheral vm45/p30 regosc regcpu gnd0 v osc v cpu rx0/p121 tx0/p120 intp0/p00 to intp7/p07 beep0/p36 buz/p37 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 10 port 12 port 13 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p77 p100 to p102 p120 to p124 p130 to p137 amifc/p101 fmifc/p102 eo0 eo1 vcol vcoh v dd pll gndpll av dd av ss ic gnd2 gnd1 78k/0 cpu core rom pd178098a: 60 kb pd178096a: 48 kb ram pd178098a: 3 kb pd178096a: 2 kb 38 chapter 1 outline user s manual u12790ej2v0ud (3) pd178f098 16-bit timer/ event counter 8-bit timer/ event counter 50 8-bit timer/ event counter 51 watchdog timer basic timer serial interface 0 serial interface 1 iebus 0 interrupt control buzzer output system control 78k/0 cpu core flash memory (60 kb) 8 8 8 8 8 8 8 8 8 3 5 8 8 p00 to p07 a/d converter ani0/p10 to ani7/p17 frequency counter pll voltage regulator pll voltage regulator ti00/p32 ti01/p33 to0/p31 ti50/p34 to50/p130 ti51/p35 to51/p131 si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 serial interface 3 si3/p70 so3/p71 sck3/p72 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 reset x1 x2 v dd port gndport v dd reset cpu peripheral vm45/p30 regosc regcpu gnd0 v osc v cpu rx0/p121 tx0/p120 uart0 rxd0/p74 txd0/p75 intp0/p00 to intp7/p07 beep0/p36 buz/p37 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 10 port 12 port 13 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p77 p100 to p102 p120 to p124 p130 to p137 amifc/p101 fmifc/p102 eo0 eo1 vcol vcoh v dd pll gndpll av dd av ss ic gnd2 gnd1 ram (3 kb) 39 chapter 1 outline user s manual u12790ej2v0ud 1.7 functional outline (1/2) item pd178076 pd178078 pd178096a pd178098a pd178f098 internal rom 48 kb 60 kb 48 kb 60 kb 60 kb memory (mask rom) (mask rom) (mask rom) (mask rom) (flash memory) high-speed ram 1024 bytes buffer ram 32 bytes expansion ram 1024 bytes 2048 bytes 1024 bytes 2048 bytes general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction 0.317 s/0.635 s/1.27 s/2.54 s/5.08 s (with crystal resonator of f x = 6.3 mhz) execution time 0.444 s/0.889 s/1.778 s/3.556 s/7.111 s (with crystal resonator of f x = 4.5 mhz) note 1 instruction set 16-bit operation multiplication/division (8 bits 8 bits, 16 bits 8 bits) bit manipulation (set, reset, test, boolean operation) bcd adjustment, etc. i/o ports total: 80 pins cmos input: 8 pins cmos i/o: 64 pins n-ch open-drain output: 8 pins a/d converter 8-bit resolution 8 channels serial interface 3-wire/sbi/2-wire/i 2 c bus note 2 mode selectable: 1 channel 3-wire mode: 1 channel 3-wire mode (with automatic transmit/receive function of up to 32 bytes): 1 channel uart mode: 1 channel iebus controller not provided provided timer basic timer (timer carry ff (10 hz)): 1 channel 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watchdog timer: 1 channel buzzer output beep0 pin: 1 khz, 1.5 khz, 3 khz, 4 khz buz pin: 0.77 khz, 1.54 khz, 3.08 khz, 6.15 khz (with crystal resonator of f x = 6.3 mhz) notes 1. when using the iebus controller of the pd178096a, 178098a or 178f098, the 4.5 mhz crystal resonator cannot be used. use the 6.3 mhz crystal resonator. 2. when the i 2 c bus mode is used (including when the mode is implemented in software without using the peripheral hardware), consult nec electronics when ordering a mask. 3-wire/sbi/2-wire/i 2 c bus note 2 mode selectable: 1 channel 3-wire mode: 1 channel 3-wire mode (with automatic transmit/receive function of up to 32 bytes): 1 channel 3-wire/sbi/2-wire/ i 2 c bus note 2 mode selectable: 1 channel 3-wire mode: 1 channel 3-wire mode (with automatic transmit/ receive function of up to 32 bytes): 1 channel uart mode: 1 channel 40 chapter 1 outline user? manual u12790ej2v0ud (2/2) item pd178076 pd178078 pd178096a pd178098a pd178f098 vectored maskable internal: 13 internal: 12 internal: 15 interrupt external: 8 external: 8 external: 8 sources non-maskable internal: 1 software 1 pll division mode 2 types frequency ?direct division mode (vcol pin) synthesizer ?pulse swallow mode (vcol and vcoh pins) reference seven types selectable by software (1, 3, 9, 10, 12.5, 25, 50 khz) frequency charge pump error out output: 2 pins phase unlock detectable in software comparator frequency counter frequency measurement amifc pin: for 450 khz counting fmifc pin: for 450 khz/10.7 mhz counting standby function halt mode stop mode reset reset by reset pin internal reset by watchdog timer reset by power-on clear circuit ?detection of less than 4.5 v note (reset does not occur) ?detection of less than 3.5 v note (during cpu operation) ?detection of less than 2.3 v note (in stop mode) supply voltage v dd = 4.5 to 5.5 v (during cpu, pll operation) ? dd = 3.5 to 5.5 v (during cpu operation) package 100-pin plastic qfp (14 20 mm, 0.65 mm pitch) note for details, refer to chapter 22 reset function . 41 user? manual u12790ej2v0ud chapter 2 pin functions 2.1 pin function list (1) port pins (1/2) pin name i/o function after reset alternate function p00 to p07 i/o port 0. input intp0 to intp7 8-bit i/o port. can be set to input or output mode in 1-bit units. p10 to p17 input port 1. input ani0 to ani7 8-bit input port. p20 i/o port 2. input si1 p21 8-bit i/o port. so1 p22 can be set to input or output mode in 1-bit units. sck1 p23 stb p24 busy p25 si0/sb0/sda0 p26 so0/sb1/sda1 p27 sck0/scl p30 i/o port 3. input vm45 p31 8-bit i/o port. to0 p32 can be set to input or output mode in 1-bit units. ti00 p33 ti01 p34 ti50 p35 ti51 p36 beep0 p37 buz p40 to 47 i/o port 4. input 8-bit i/o port. can be set to input or output mode in 1-bit units. p50 to p57 i/o port 5. input 8-bit i/o port. can be set to input or output mode in 1-bit units. p60 to p67 i/o port 6. input 8-bit i/o port. can be set to input or output mode in 1-bit units. p70 i/o port 7. input si3 p71 8-bit i/o port. so3 p72 can be set to input or output mode in 1-bit units. sck3 p73 p74 rxd0 note p75 txd0 note p76, p77 note pd178076, 178078, and 178f098 only. 42 chapter 2 pin functions user? manual u12790ej2v0ud (1) port pins (2/2) pin name i/o function after reset alternate function p100 i/o port 10. input p101 3-bit i/o port. amifc p102 can be set to input or output mode in 1-bit units. fmifc p120 i/o port 12. input tx0 note p121 5-bit i/o port. rx0 note p122 to p124 can be set to input or output mode in 1-bit units. p130 output port 13. low level to50 p131 8-bit output port. output to51 p132 to p137 n-ch open-drain output port (12 v tolerant) note pd178096a, 178098a, and 178f098 only. (2) non-port pins (1/2) pin name i/o function after reset alternate function intp0 to input external maskable interrupt input whose valid edge input p00 to p07 intp7 (rising edge, falling edge, or both rising and falling edges) can be specified. si0 input serial data input to serial interface. input p25/sb0/sda0 si1 p20 si3 p70 so0 output serial data output from serial interface. input p26/sb1/sda1 so1 p21 so3 p71 sb0 i/o serial data input/output to/from n-ch open-drain i/o input p25/si0/sda0 sb1 serial interface. p26/so0/sda1 sda0 p25/si0/sb0 sda1 p26/so0/sb1 sck0 i/o serial clock input/output to/from serial interface. input p27/scl sck1 p22 sck3 p72 scl n-ch open-drain i/o p27/sck0 stb output strobe output for serial interface automatic transmission/ input p23 reception. busy input busy input for serial interface automatic transmission/ input p24 reception. vw45 output v dd = 4.5 v monitor output input p30 ti00 input external count clock input to 16-bit timer (tm0). input p32 ti01 p33 ti50 input external count clock input to 8-bit timer (tm50). input p34 ti51 external count clock input to 8-bit timer (tm51). p35 43 chapter 2 pin functions user? manual u12790ej2v0ud (2) non-port pins (2/2) pin name i/o function after reset alternate function to0 output 16-bit timer (tm0) output. input p31 to50 8-bit timer (tm50) output. low level p130 to51 8-bit timer (tm51) output. output p131 beep0 output buzzer output. input p36 buz p37 ani0 to ani7 input analog input to a/d converter. input p10 to p17 eo0, eo1 output error out output from charge pump of pll frequency synthesizer. vcol input inputs local oscillation frequency of pll (in hf and mf modes). vcoh input inputs local oscillation frequency of pll (in vhf mode). amifc input input to am intermediate frequency counter. input p101 fmifc input input to fm intermediate frequency or am intermediate input p102 frequency counter. rxd0 note 1 input serial data input to asynchronous serial interface (uart0). input p74 txd0 note 1 output serial data output from asynchronous serial interface (uart0). input p75 tx0 note 2 output iebus controller data output. input p120 rx0 note 2 input iebus controller data input. input p121 reset input system reset input. x1 input connection of crystal resonator for system clock oscillation. x2 regosc regulator for oscillator. connect this pin to gnd via a 0.1 f capacitor. regcpu regulator for cpu power supply. connect this pin to gnd via a 0.1 f capacitor. v dd positive power supply. gnd0 to gnd2 ground. v dd port port power supply. make the same potential as v dd . gndport port ground. make the same potential as gnd0 to gnd2. av dd a/d converter positive power supply. make the same potential as v dd . av ss a/d converter ground. make the same potential as gnd0 to gnd2. v dd pll note 4 pll positive power supply. make the same potential as v dd . gndpll note 4 pll ground. make the same potential as gnd0 to gnd2. ic internally connected. directly connect this pin to gnd0, gnd1, or gnd2. v pp note 3 pin to apply high voltage at program write/verify. notes 1. pd178076, 178078, and 178f098 only. 2. pd178096a, 178098a, and 178f098 only. 3. pd178f098 only. 4. connect a capacitor of about 1000 pf between the v dd pll and gndpll pins. 44 chapter 2 pin functions user? manual u12790ej2v0ud 2.2 description of pin functions 2.2.1 p00 to p07 (port 0) these are 8-bit i/o port pins. besides serving as i/o port pins, they also function as external interrupt inputs. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as an 8-bit i/o port that can be set to input or output mode in 1-bit units using port mode register 0. (2) control mode these pins function as external interrupt input pins (intp0 to intp7). intp0 to intp7 are external interrupt input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.2 p10 to p17 (port 1) these are 8-bit input port pins. besides serving as input port pins, they also function as a/d converter analog inputs. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as an 8-bit input port. (2) control mode these pins function as a/d converter analog input pins (ani0 to ani7). 2.2.3 p20 to p27 (port 2) these are 8-bit i/o port pins. besides serving as i/o port pins, they also have serial interface data input/output, clock i/o, automatic transmit/receive busy input, and strobe output functions. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as an 8-bit i/o port that can be set to input or output mode in 1-bit units using port mode register 2. (2) control mode these pins function as serial interface data i/o, clock i/o, automatic transmit/receive busy input, and strobe output pins. (a) si0, si1, so0, so1, sda0 note , sda1 note these are serial interface serial data i/o pins. sda0 and sda1 are n-ch open drain. (b) sck0 and sck1, scl note these are serial interface serial clock i/o pins. scl is n-ch open drain. note for i 2 c bus mode 45 chapter 2 pin functions user? manual u12790ej2v0ud (c) sb0 and sb1 these are nec standard serial bus interface i/o pins. sb0 and sb1 are n-ch open drain. (d) busy this is the serial interface automatic transmit/receive busy input pin. (e) stb this is the serial interface automatic transmit/receive strobe output pin. caution when this port is used for the serial interface, the i/o and output latches must be set according to the required function. for the setting, refer to table 4-3 port mode register and output latch settings when using alternate functions and figure 13-5 format of serial operating mode register 0 (csim0). 2.2.4 p30 to p37 (port 3) these are 8-bit i/o port pins. beside serving as i/o port pins, they also have v dd = 4.5 v monitor output, timer output, timer input and buzzer output functions. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as an 8-bit i/o port that can be set to input or output mode in 1-bit units using port mode register 3. (2) control mode these pins function as v dd = 4.5 v monitor output, timer output, timer input, and buzzer (beep0, buz) output pins. (a) vm45 this is the monitor output pin of v dd = 4.5 v. (b) to0 this is the output pin of the 16-bit timer/event counter. (c) ti00 this is the external count clock input pin of the 16-bit timer/event counter and a capture trigger signal input pin. (d) ti01 this is a capture trigger signal input pin of the 16-bit timer/event counter. (e) ti50, ti51 these are pins for external clock input to the 8-bit timer/event counter. (f) beep0, buz these are buzzer output pins. 2.2.5 p40 to p47 (port 4) these are 8-bit i/o port pins. they can be set to input or output mode in 8-bit units mode using port mode register 4. 46 chapter 2 pin functions user? manual u12790ej2v0ud 2.2.6 p50 to p57 (port 5) these are 8-bit i/o port pins. they can be set to input or output mode in 1-bit units using port mode register 5. 2.2.7 p60 to p67 (port 6) these are 8-bit i/o port pins. they can be set to input or output mode in 1-bit units using port mode register 6. 2.2.8 p70 to p77 (port 7) these are 8-bit i/o port pins. besides serving as i/o port pins, they also have serial interface data i/o, clock i/o, and asynchronous serial interface data i/o functions. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as an 8-bit i/o port that can be set to input or output mode in 1-bit units using port mode register 7. (2) control mode these pins function as serial interface data i/o, clock i/o, and asynchronous serial interface data i/o pins. (a) si3 and so3 these are serial data i/o pins of the serial interface. (b) sck3 this is a serial clock i/o pin of the serial interface. (c) rxd0, txd0 ( pd178076, 178078, and 178f098 only) these are serial data i/o pins of the asynchronous serial interface. 2.2.9 p100 to p102 (port 10) these are 3-bit i/o port pins. besides serving as i/o port pins, they can also be used as the input pins of an am intermediate frequency counter and an fm intermediate frequency counter. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as a 3-bit i/o port that can be set to input or output mode in 1-bit units using port mode register 10. (2) control mode these pins can be used as the input pins of the am intermediate frequency counter and fm intermediate frequency counter. (a) amifc this is an input pin of the am intermediate frequency counter. (b) fmifc this is an input pin of the fm intermediate frequency counter or am intermediate frequency counter. 47 chapter 2 pin functions user? manual u12790ej2v0ud 2.2.10 p120 to p124 (port 12) these pins are 5-bit i/o port pins that can also be used to input iebus data. they can be set to input or output mode in 1-bit units using port mode register 12. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as a 5-bit i/o port that can be set to input or output mode in 1-bit units using port mode register 12. (2) control mode ( pd178096a, 178098a, and 178f098 only) these pins can be used as the iebus controller data i/o (rx0 and tx0). 2.2.11 p130 to p137 (port 13) these are 8-bit output port pins. they are n-ch open-drain pins with a 12 v withstanding voltage. besides serving as output port pins, they are used for timer output. the following operating modes can be specified in 1-bit units. (1) port mode these pins function as an 8-bit output port. (2) control mode these pins function as outputs for the 8-bit timer/event counter (to50, to51). 2.2.12 eo0, eo1 these are the output pins of the charge pump of the pll frequency synthesizer. they output the result of phase comparison between the frequency divided by the programmable divider of the local oscillation input (vcol and vcoh pins) and the reference frequency. 2.2.13 vcol, vcoh these pins input the local oscillation frequency (vco) of the pll. because signals are input to these pins via an ac amplifier, cut the dc component of the input signals by using a capacitor. vcol hf, mf input this pin becomes active when the hf or mf mode is selected by software. otherwise, the pin is in the status set by bit 2 (vcoldmd) of the pll mode select register (pllmd). if vcoldmd is reset to 0 (to connect a pull-down resistor), however, the vcol pin does not become active even if the hf or mf mode is selected. in this case, set vcoldmd to 1 (high-impedance state). vcoh vhf input this pin becomes active when the fm mode is selected by software. otherwise, the pin is in the status set by bit 3 (vcohdmd) of the pll mode select register (pllmd). if vcohdmd is reset to 0 (to connect a pull-down resistor), however, the vcoh pin does not become active even if the fm mode is selected. in this case, set vcohdmd to 1 (high-impedance state). 2.2.14 reset this is a low-level active system reset input pin. 48 chapter 2 pin functions user? manual u12790ej2v0ud 2.2.15 x1, x2 these are crystal resonator connection pins for system clock oscillation. 2.2.16 regosc this is the oscillator regulator pin. connect to gnd via a 0.1 f capacitor. 2.2.17 regcpu this is the cpu power supply regulator pin. connect to gnd via a 0.1 f capacitor. 2.2.18 v dd this is the positive power supply pin. 2.2.19 gnd0 to gnd2 these are ground potential pins. 2.2.20 v dd port this is the positive power supply pin for ports. 2.2.21 gndport this is the ground potential pin for ports. 2.2.22 v dd pll this is the positive power supply pin for the pll. 2.2.23 gndpll this is the ground potential pin for the pll. 2.2.24 av dd this is the analog power supply pin of the a/d converter. always keep the voltage on this pin at the same level as that on the v dd pin even when the a/d converter is not used. 2.2.25 av ss this is the ground pin of the a/d converter. always keep the voltage on this pin at the same level as that on the gnd0, gnd1, or gnd2 pin even when the a/d converter is not used. 2.2.26 v pp ( pd178f098 only) this pin applies a high voltage when the flash memory programming mode is set or when a program is written or verified. connect this pin in either of the following ways. connect independently to a 10 k ? pull-down resistor. by using a jumper on the board, connect directly to the dedicated flash programmer in the programming mode or to gnd in the normal operation mode. when the wiring between the v pp pin and gnd pin is long or external noise is input to the v pp pin, the user? program may not run normally. 49 chapter 2 pin functions user? manual u12790ej2v0ud 2.2.27 ic (mask rom versions only) the ic (internally connected) pin is provided to set the test mode to check the pd178078 and 178098a subseries at delivery. connect it directly to the gnd pin with the shortest possible wire in the normal operating mode. when a potential difference is produced between the ic pin and gnd pin because the wiring between the two pins is too long or external noise is input to the ic pin, the user's program may not run normally. connect ic pin to gnd pin directly. gnd ic as short as possible 50 chapter 2 pin functions user s manual u12790ej2v0ud 2.3 pin i/o circuits and recommended connection of unused pins table 2-1 shows the pin i/o circuit types and the recommended connection of the pins when they are not used. for the configuration of the i/o circuit of each pin, refer to figure 2-1. table 2-1. pin i/o circuit types (1/2) pin name i/o circuit type i/o recommended connection of unused pin p00/intp0 to p07/intp7 8 i/o input: independently connect to v dd , v dd port, gnd0 to gnd2, or gndport via a resistor. output: leave open. p10/ani0 to p17/ani7 25 input directly connect to v dd , v dd port, gnd0 to gnd2, or gndport. p20/si1 5-k i/o input: independently connect to v dd , v dd port, gnd0 p21/so1 5 to gnd2, or gndport via a resistor. p22/sck1 5-k output: leave open. p23/stb 5 p24/busy 5-k p25/si0/sb0/sda0 10-d p26/so0/sb1/sda1 p27/sck0/scl p30/vm45 5 p31/to0 p32/ti00 5-k p33/ti01 p34/ti50 p35/ti51 p36/beep0 5 p37/buz p40 to p47 p50 to p57 p60 to p67 p70/si3 5-k p71/so3 5 p72/sck3 5-k p73 5 p74/rxd0 5-k p75/txd0 5 p76, p77 p100 p101/amifc p102/fmifc p120/tx0 p121/rx0 5-k p122 to p124 5 51 chapter 2 pin functions user? manual u12790ej2v0ud table 2-1. pin i/o circuit types (2/2) pin name i/o circuit type i/o recommended connection of unused pin p130/to50 19 output leave open. p131/to51 p132 to p137 eo0 dts-eo1 eo1 vcol, vcoh dts-amp2 input disable pll by software and select pull-down. regosc, regcpu connect to gnd0, gnd1, or gnd2 via 0.1 f capacitor. reset 2 input av dd connect to v dd or v dd port. av ss directly connect to gnd0 to gnd2, or gndport. ic (mask rom version) v pp (flash memory version) independently connect a 10 k ? pull-down resistor or di- rectly connect to gnd0, gnd1, gnd2, or gndport. 52 chapter 2 pin functions user s manual u12790ej2v0ud figure 2-1. pin i/o circuits (1/2) remark v dd and gnd are the positive power supply and ground pins for all port pins. read v dd and gnd as v dd port and gndport. in data output disable p-ch in/out v dd n-ch input enable data output disable p-ch in/out v dd n-ch input enable data output disable p-ch in/out v dd n-ch data p-ch in/out v dd n-ch input enable open drain output disable out n-ch type 2 type 5 type 5-k type 8 type 10-d type 19 schmitt-triggered input with hysteresis characteristics 53 chapter 2 pin functions user s manual u12790ej2v0ud figure 2-1. pin i/o circuits (2/2) note this switch is selectable by software only for the vcol and vcoh pins. remark v dd and gnd are the positive power supply and ground pins for all port pins. read v dd and gnd as v dd port and gndport. dw up p-ch out v dd pll gndpll n-ch input enable + n-ch p-ch in comparator v ref (threshold voltage) in v dd pll gndpll note type 25 type dts-amp type dts-eo1 54 users manual u12790ej2v0ud chapter 3 cpu architecture 3.1 memory spaces the initial values of the memory size select register (ims) and internal expansion ram size select register (ixs) are cfh and 0ch, respectively. the following values must be set to the registers of each product. part number ims ixs pd178076, 178096a cch 0ah pd178078, 178098a cfh 08h pd178f098 value equivalent to mask value equivalent to mask rom version rom version 55 chapter 3 cpu architecture users manual u12790ej2v0ud (1) pd178076, 178096a set the values of the memory size select register (ims) and internal expansion ram size select register (ixs) to cch and 0ah, respectively (the initial values are cfh and 0ch). figure 3-1. memory map ( pd178076, 178096a) special-function registers (sfrs) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits buffer ram 32 8 bits use prohibited use prohibited use prohibited internal expansion ram 1024 8 bits internal rom 49152 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area ffffh 0000h ff00h feffh fee0h fedfh fb00h faffh fae0h fadfh fac0h fabfh f800h f7ffh f400h f3ffh c000h bfffh 0000h bfffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 56 chapter 3 cpu architecture user s manual u12790ej2v0ud (2) pd178078, 178098a set the values of the memory size select register (ims) and internal expansion ram size select register (ixs) to cfh and 08h, respectively (the initial values are cfh and 0ch). figure 3-2. memory map ( pd178078, 178098a) ffffh 0000h ff00h feffh fee0h fedfh fb00h faffh fae0h fadfh fac0h fabfh f800h f7ffh f000h efffh 0000h efffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh special-function registers (sfrs) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits buffer ram 32 8 bits use prohibited use prohibited internal expansion ram 2048 8 bits internal rom 61440 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area 57 chapter 3 cpu architecture user s manual u12790ej2v0ud (3) pd178f098 set the value of the memory size select register (ims) and internal expansion ram size select register (ixs) to the value corresponding to that of the mask rom versions (the initial values are cfh and 0ch). figure 3-3. memory map ( pd178f098) ffffh 0000h ff00h feffh fee0h fedfh fb00h faffh fae0h fadfh fac0h fabfh f800h f7ffh f000h efffh 0000h efffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh special-function registers (sfrs) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits buffer ram 32 8 bits use prohibited use prohibited internal expansion ram 2048 8 bits flash memory 61440 8 bits program memory space data memory space vector table area callt table area program area callf entry area program area 58 chapter 3 cpu architecture user s manual u12790ej2v0ud 3.1.1 internal program memory space the internal program memory space stores programs and table data, and is usually addressed by the program counter (pc). the pd178078, 178098a subseries products incorporate the following internal rom (or flash memory). table 3-1. internal memory capacity product structure capacity pd178076, 178078 mask rom 49152 8 bits (0000h to bfffh) pd178096a, 178098a 61440 8 bits (0000h to efffh) pd178f098 flash memory (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. the reset input and program start addresses for branch upon generation of an interrupt request are stored in the vector table area. of the 16- bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. table 3-2. vector table vector table address interrupt request vector table address interrupt request 0000h reset input 001ch inttm50 0004h intwdt 001eh inttm51 0006h intp0 0020h intser0 note 1 0008h intp1 0022h intsr0 note 1 000ah intp2 0024h intst0 note 1 000ch intp3 0026h intbtm0 000eh intp4 0028h inttm00 0010h intp5 002ah inttm01 0012h intp6 002ch intie1 note 2 0014h intp7 002eh intie2 note 2 0016h intcsi0 0030h intad 0018h intcsi1 003eh brk 001ah intcsi3 notes 1. pd178076, 178078, and 178f098 only. 2. pd178096a, 178098a, and 178f098 only. (2) callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of a 1-byte call instruction (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf). 59 chapter 3 cpu architecture user s manual u12790ej2v0ud 3.1.2 internal data memory space the pd178078 and 178098a subseries products incorporate the following rams. (1) internal high-speed ram a high-speed memory of 1024 bytes is incorporated. in this area, four banks of general-purpose registers, each bank consisting of eight 8-bit registers, are allocated in the 32-byte area fee0h to feffh. this area cannot be used as a program area to which instructions are written and executed. the internal high-speed ram can also be used as a stack memory area. (2) buffer ram buffer ram is allocated to the 32-byte area from fac0h to fadfh. buffer ram is used to store transmit/ receive data for serial interface channel 1 (3-wire serial i/o mode with automatic transmit/receive function). when not used in this mode, buffer ram can also be used as normal ram. (3) internal expansion ram internal expansion ram is allocated to the 1024-byte area from f400h to f7ffh in the pd178076 and 178096a. for the pd178078, 178098a, and 178f098, it is allocated to the 2048-byte area from f000h to f7ffh. this area can be used as a normal data area like the internal high-speed ram, and also as a program area to which instructions are written and executed. the internal expansion ram cannot be used as a stack memory. 3.1.3 special-function register (sfr) area on-chip peripheral hardware special-function registers (sfrs) are allocated in the area ff00h to ffffh. (refer to table 3-4 special-function registers .) caution do not access addresses where an sfr is not assigned. 60 chapter 3 cpu architecture user s manual u12790ej2v0ud 3.1.4 data memory addressing the method to specify the address of the instruction to be executed next, or the address of a register or memory to be manipulated when an instruction is executed is called addressing. to address the memory that is manipulated when an instruction is executed, the pd178078, 178098a subseries products are provided with many addressing modes to enable high operability. especially at addresses corresponding to data memory area, particular addressing modes can be used in accordance with the functions of the special-function registers (sfrs) and general-purpose registers. figures 3-4 to 3-6 show the data memory addressing modes. for details of each addressing, see 3.4 operand address addressing. figure 3-4. correspondence between data memory and addressing ( pd178076, 178096a) ffffh ff20h ff1fh ff00h feffh fee0h fedfh fe20h fe1fh fb00h faffh fae0h fadfh fac0h fabfh f800h f7ffh f400h f3ffh c000h bfffh 0000h special-function registers (sfrs) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits buffer ram 32 8 bits use prohibited use prohibited use prohibited internal expansion ram 1024 8 bits internal rom 49152 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing 61 chapter 3 cpu architecture user s manual u12790ej2v0ud figure 3-5. correspondence between data memory and addressing ( pd178078, 178098a) ffffh ff20h ff1fh ff00h feffh fee0h fedfh fe20h fe1fh fb00h faffh fae0h fadfh fac0h fabfh f800h f7ffh f000h efffh 0000h special-function registers (sfrs) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits buffer ram 32 8 bits use prohibited use prohibited internal expansion ram 2048 8 bits internal rom 61440 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing 62 chapter 3 cpu architecture user s manual u12790ej2v0ud figure 3-6. correspondence between data memory and addressing ( pd178f098) ffffh ff20h ff1fh ff00h feffh fee0h fedfh fe20h fe1fh fb00h faffh fae0h fadfh fac0h fabfh f800h f7ffh f000h efffh 0000h special-function registers (sfrs) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits buffer ram 32 8 bits use prohibited use prohibited internal expansion ram 2048 8 bits flash memory 61440 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing 63 chapter 3 cpu architecture user s manual u12790ej2v0ud 3.2 processor registers the pd178078 and 178098a subseries products incorporate the following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw), and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit register that holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-7. configuration of program counter (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. the program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically restored upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 3-8. configuration of program status word pc15 pc pc14 pc13 pc12 pc11 pc9 pc8 15 0 pc10 pc7 pc6 pc5 pc4 pc3 pc1 pc0 pc2 70 ie z rbs1 ac rbs0 0 isp cy psw 64 chapter 3 cpu architecture user s manual u12790ej2v0ud (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledgment operations of the cpu. when ie = 0, all the interrupts are disabled (di) except the non-maskable interrupt. when ie = 1, the interrupts are enabled (ei). at this time, the acknowledgment of interrupts is controlled by the in-service priority flag (isp), the interrupt mask flag corresponding to each interrupt, and the interrupt priority specification flag. the ie flag is reset to (0) upon di instruction execution or interrupt acknowledgment and is set to (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. the 2-bit information that indicates the register bank selected by sel rbn instruction execution is stored in these flags. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable maskable vectored interrupts. when isp = 0, acknowledging the vectored interrupt requests to which a low priority is assigned by the priority specification flag registers (pr0l, pr0h, pr1l) (refer to 18.3 (3) priority specification flag registers (pr0l, pr0h, pr1l) ) is disabled. whether an interrupt request is actually acknowledged depends on the status of the interrupt enable flag (ie). (f) carry flag (cy) this flag stores an overflow and underflow upon add/subtract instruction execution. it stores the shift- out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. 65 chapter 3 cpu architecture user s manual u12790ej2v0ud (3) stack pointer (sp) this is a 16-bit register that holds the start address of the memory stack area. only the internal high-speed ram area (fb00h to feffh) can be set as the stack area. figure 3-9. configuration of stack pointer the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. each stack operation saves/restores data as shown in figures 3-10 and 3-11. caution since reset input makes the sp contents undefined, be sure to initialize the sp before instruction execution. sp15 sp sp14 sp13 sp12 sp11 sp9 sp8 15 0 sp10 sp7 sp6 sp5 sp4 sp3 sp1 sp0 sp2 66 chapter 3 cpu architecture user? manual u12790ej2v0ud figure 3-10. data to be saved to stack memory (a) push rp instruction (when sp is fee0h) (b) call, callf, callt instructions (when sp is fee0h) (c) interrupt, brk instructions (when sp is fee0h) fee0h fee0h fedfh fedeh pc15 to pc8 pc7 to pc0 fedeh sp sp fee0h fee0h fedfh fedeh psw pc15 to pc8 feddh sp sp feddh pc7 to pc0 fee0h higher register pair lower register pair fedeh sp sp fee0h fedfh fedeh 67 chapter 3 cpu architecture user s manual u12790ej2v0ud figure 3-11. data to be restored from stack memory (a) pop rp instruction (when sp is fedeh) (b) ret instruction (when sp is fedeh) (c) reti, retb instructions (when sp is feddh) fee0h higher register pair lower register pair fedeh sp sp fee0h fedfh fedeh fee0h fee0h fedfh fedeh pc15 to pc8 pc7 to pc0 fedeh sp sp fee0h fee0h fedfh fedeh psw pc15 to pc8 feddh sp sp feddh pc7 to pc0 68 chapter 3 cpu architecture user s manual u12790ej2v0ud 3.2.2 general-purpose registers general-purpose registers are mapped at particular addresses (fee0h to feffh) of the data memory. they consist of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l and h). each register can be used as an 8-bit register, and two 8-bit registers can also be used in pairs as a 16-bit register (ax, bc, de and hl). they can be written using function names (x, a, c, b, e, d, l, h, ax, bc, de and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set by the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupt for each bank. table 3-3. absolute addresses of general-purpose registers bank register absolute function name absolute name address bank0 h r7 f e f f h lr6fefeh dr5fefdh er4fefch br3fefbh cr2fefah ar1fef9h xr0fef8h bank1 h r7 f e f 7 h lr6fef6h dr5fef5h er4fef4h br3fef3h cr2fef2h ar1fef1h xr0fef0h bank register absolute function name absolute name address bank2 h r7 f e e f h l r6 feeeh dr5feedh er4feech b r3 feebh c r2 feeah ar1fee9h xr0fee8h bank3 h r7 f e e 7 h lr6fee6h dr5fee5h er4fee4h br3fee3h cr2fee2h ar1fee1h xr0fee0h 69 chapter 3 cpu architecture user s manual u12790ej2v0ud figure 3-12. general-purpose register configuration (a) absolute name (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fee0h fee8h bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h 70 chapter 3 cpu architecture user s manual u12790ej2v0ud 3.2.3 special-function registers (sfr) unlike a general-purpose register, each special function register has a special function. special-function registers are allocated in the area ff00h to ffffh. special-function registers can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. the manipulatable bit units, 1, 8 and 16, depend on the special-function register type. each bit manipulation unit can be specified as follows. ? 1-bit manipulation use the symbol reserved in the assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation use the symbol reserved in the assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation use the symbol reserved in the assembler for the 16-bit manipulation instruction operand (sfrp). when addressing an address, use an even address. table 3-4 gives a list of special-function registers. the meanings of items in the table are as follows. ? symbol this is a symbol to indicate the address of the special-function register. these symbols are reserved in the df178098 and ra78k0, and defined by the header file sfrbit.h in the cc78k0. they can be written as instruction operands when the ra78k0, id78k0, id78k0-ns, id78k0-ns-a, or sm78k0 is used. ? r/w indicates whether the corresponding special-function register can be read or written. r/w: read/write enabled r: read only r&reset: read only (reset to 0 when read) w: write only ? manipulatable bits indicates the manipulatable bit units 1, 8, and 16. C indicates the bit units that cannot be manipulated. ? after reset indicates the status of each register upon reset. the values of special-function registers whose addresses are not shown in the table are undefined after reset. 71 chapter 3 cpu architecture users manual u12790ej2v0ud table 3-4. special-function registers (1/4) address special-function register (sfr) name symbol r/w manipulatable bits after reset 1816 ff00h port 0 p0 r/w 00h ff01h port 1 p1 r undefined ff02h port 2 p2 r/w 00h ff03h port 3 p3 ff04h port 4 p4 ff05h port 5 p5 ff06h port 6 p6 ff07h port 7 p7 ff0ah port 10 p10 ff0ch port 12 p12 ff0dh port 13 p13 ff10h a/d conversion result register 3 note 1 adcr3 ff11h r undefined ff12h a/d converter mode register 3 adm3 r/w 00h ff13h analog input channel specification register 3 ads3 ff15h power-fail comparison threshold value register 3 pft3 ff16h power-fail comparison mode register 3 pfm3 ff19h vm45 control register vm45c ff1ah serial i/o shift register 0 sio0 undefined ff1bh poc status register pocs r&reset held note 2 ff20h port mode register 0 pm0 r/w ffh ff22h port mode register 2 pm2 ff23h port mode register 3 pm3 ff24h port mode register 4 pm4 ff25h port mode register 5 pm5 ff26h port mode register 6 pm6 ff27h port mode register 7 pm7 ff2ah port mode register 10 pm10 ff2ch port mode register 12 pm12 ff40h clock output select register cks 00h ff41h beep frequency select register 0 beepcl0 ff42h watchdog timer clock select register wdcs ff43h serial interface clock select register 0 scl0 08h ff48h external interrupt rising edge enable register egp 00h ff49h external interrupt falling edge enable register egn notes 1. this register can be accessed only in 8-bit units. when adcr3 is read, the value of ff11h is read. 2. the value of this register is 03h only after reset by power-on clear. this register is not reset by the reset pin or watchdog timer. caution do not access addresses to which no sfr is assigned. 72 chapter 3 cpu architecture users manual u12790ej2v0ud table 3-4. special-function registers (2/4) address special-function register (sfr) name symbol r/w manipulatable bits after reset 1816 ff5ah asynchronous serial interface mode register 0 note asim0 r/w 00h ff5bh asynchronous serial interface status register 0 note asis0 r ff5ch baud rate generator control register 0 note brgc0 r/w ff5dh transmit shift register 0 note txs0 w ffh receive buffer register 0 note rxb0 r ffh ff60h serial operating mode register 0 csim0 r/w 00h ff61h serial bus interface control register 0 sbic0 ff62h slave address register 0 sva0 undefined ff63h interrupt timing specification register 0 sint0 00h ff67h serial i/o shift register 1 sio1 undefined ff68h serial operating mode register 1 csim1 00h ff69h automatic data transmit/receive address pointer adtp ff6ah automatic data transmit/receive control register adtc ff6bh automatic data transmit/receive interval specification adti register ff6eh serial i/o shift register 3 sio3 undefined ff6fh serial operating mode register 3 csim3 00h ff70h 16-bit timer counter 0 tm0 r 0000h ff71h ff72h 16-bit capture/compare register 00 cr00 r/w undefined ff73h ff74h 16-bit capture/compare register 01 cr01 ff75h ff78h 16-bit timer mode control register 0 tmc0 00h ff7ah prescaler mode register 0 prm0 ff7ch capture/compare control register 0 crc0 ff7eh 16-bit timer output control register 0 toc0 ff80h 8-bit compare register 50 cr50 undefined ff81h 8-bit compare register 51 cr51 ff82h 8-bit timer counter 50 tm5 tm50 r 00h ff83h 8-bit timer counter 51 tm51 ff84h timer clock select register 50 tcl50 r/w ff85h 8-bit timer mode control register 50 tmc50 ff87h timer clock select register 51 tcl51 ff88h 8-bit timer mode control register 51 tmc51 ffa0h pll mode select register pllmd ffa1h pll reference mode register pllrf 0fh note pd178076, 178078, and 178f098 only caution do not access addresses to which no sfr is assigned. CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 73 chapter 3 cpu architecture user? manual u12790ej2v0ud table 3-4. special-function registers (3/4) address special-function register (sfr) name symbol r/w manipulatable bits after reset 1816 ffa2h pll unlock f/f judge register pllul r&reset undefined ffa3h pll data transfer register pllns w 00h ffa6h pll data registers pll data register l pllr pllrl r/w undefined ffa7h pll data register h pllrh ffa8h pll data register 0 pllr0 ffa9h if counter mode select register ifcmd 00h ffaah dts system clock select register dtsck ffabh if counter gate judge register ifcjg r ffach if counter control register ifccr w ffaeh if counter register ifcr ifcrl r ffafh ifcrh ffb0h iebus control register 0 note 1 bcr0 r/w ffb2h iebus unit address register note 1 uar uarl ffb3h uarh ffb4h iebus slave address register note 1 sar sarl ffb5h sarh ffb6h iebus partner unit address register note 1 par parl ffb7h parh ffb8h iebus control data register note 1 cdr 01h ffb9h iebus telegraph length register note 1 dlr ffbah iebus data register note 1 dr 00h ffbbh iebus unit status register note 1 usr r ffbch iebus interrupt status register note 1 isr r/w ffbdh iebus slave status register note 1 ssr r 41h ffbeh iebus communication successful counter note 1 scr 01h ffbfh iebus transmission counter note 1 ccr 20h ffd0h external access area note 2 r/w undefined | ffdfh ffe0h interrupt request flag register 0l if0 if0l 00h ffe1h interrupt request flag register 0h if0h ffe2h interrupt request flag register 1l if1l ffe4h interrupt mask flag register 0l mk0 mk0l ffh ffe5h interrupt mask flag register 0h mk0h ffe6h interrupt mask flag register 1l mk1l notes 1. pd178096a, 178098a, and 178f098 only 2. the external access area cannot be accessed by means of sfr addressing. use direct addressing to access this area. caution do not access addresses to which no sfr is assigned. 74 chapter 3 cpu architecture users manual u12790ej2v0ud table 3-4. special-function registers (4/4) address special-function register (sfr) name symbol r/w manipulatable bits after reset 1816 ffe8h priority specification flag register 0l pr0 pr0l r/w ffh ffe9h priority specification flag register 0h pr0h ffeah priority specification flag register 1l pr1l fff0h memory size select register note ims cfh note fff4h internal expansion ram size select register note ixs 0ch note fff9h watchdog timer mode register wdtm 00h fffah oscillation stabilization time select register osts 04h fffbh processor clock control register pcc note the initial values of the memory size select register (ims) and internal expansion ram size select register (ixs) are cfh and 0ch, respectively. set the values of these registers in each product as follows. part number ims ixs pd178076, 178096a cch 0ah pd178078, 178098a cfh 08h pd178f098 value corresponding to mask rom version value corresponding to mask rom version caution do not access addresses to which no sfr is assigned. 75 chapter 3 cpu architecture users manual u12790ej2v0ud 3.3 instruction address addressing an instruction address is determined by the program counter (pc) contents, which are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing. (for details of instructions, refer to the 78k/0 instruction user? manual (u12326e) .) 3.3.1 relative addressing [function] the value obtained by adding the 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed two's complement data (C128 to +127) and bit 7 becomes a sign bit. that is, using relative addressing, the program branches in the range C128 to +127 relative to the first address of the next instruction. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc jdisp8 when s = 0, all bits of are 0. when s = 1, all bits of are 1. pc indicates the start address of the instruction after the br instruction. ... 76 chapter 3 cpu architecture users manual u12790ej2v0ud 3.3.2 immediate addressing [function] the immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16, br !addr16, or callf !addr11 instruction is executed. the call !addr16 and br !add16 instructions can be used to branch to any location in the memory. the callf !addr11 instruction is used to branch to the area between 0800h and 0fffh. [illustration] in the case of the call !addr16 and br !addr16 instructions in the case of the callf !addr11 instruction 15 0 pc 87 70 fa 10 _ 8 11 10 00001 643 callf fa 7 _ 0 15 0 pc 87 70 call or br low addr. high addr. 77 chapter 3 cpu architecture users manual u12790ej2v0ud 3.3.3 table indirect addressing [function] the table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. this addressing is used when the callt [addr5] instruction is executed. this instruction references an address stored in the memory table between 40h and 7fh, and can be used to branch to any location in the memory. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4C0 operation code 78 chapter 3 cpu architecture users manual u12790ej2v0ud 3.3.4 register addressing [function] the register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87 79 chapter 3 cpu architecture users manual u12790ej2v0ud 3.4 operand address addressing the following methods are available to specify the register and memory (addressing) that undergo manipulation during instruction execution. 3.4.1 implied addressing [function] the register that functions as an accumulator (a and ax) in the general-purpose register area is automatically addressed (implied). of the pd178078 and 178098a subseries instruction words, the following instructions employ implied addressing. instruction register specified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric values which become decimal correction targets ror4/rol4 a register for storage of digit data that undergoes digit rotation [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the product of the a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing. 80 chapter 3 cpu architecture user s manual u12790ej2v0ud 3.4.2 register addressing [function] this addressing mode is used to access a general-purpose register as an operand. the register to be accessed is specified by the register bank select flags (rbs0 and rbs1) and the register specification codes (rn and rpn) in the operation code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] symbol description r x, a, c, b, e, d, l, h rp ax, bc, de, hl 'r' and 'rp' can be written using function names (x, a, c, b, e, d, l, h, ax, bc, de and hl) as well as absolute names (r0 to r7 and rp0 to rp3). [example] mov a, c; when selecting c register as r operation code 01100010 register specification code incw de; when selecting de register pair as rp operation code 10000100 register specification code 81 chapter 3 cpu architecture user s manual u12790ej2v0ud 3.4.3 direct addressing [function] the memory with immediate data in an instruction word is directly addressed. [operand format] symbol description addr16 label or 16-bit immediate data [example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 opcode 00000000 00h 11111110 feh [illustration] 70 op code addr16 (lower) addr16 (higher) memory ? ? ? ? ? 82 chapter 3 cpu architecture user? manual u12790ej2v0ud 3.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. the fixed space to which this addressing is applied is the 256-byte space fe20h to ff1fh. an internal ram and special-function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressing is applied is part of the total the sfr area. in this area, ports which are frequently accessed in a program and a compare register and a capture register of the timer/event counter are mapped and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to [ illustration ] below. [operand format] symbol description saddr label or immediate data indicating fe20h to ff1fh saddrp label or immediate data indicating fe20h to ff1fh (even addresses only) [example] mov fe30h, a; when transferring the value of register a to saddr (fe30h) operation code 11110010 opcode 00110000 30h (saddr-offset) [illustration] when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset 83 chapter 3 cpu architecture user s manual u12790ej2v0ud 3.4.5 special-function register (sfr) addressing [function] a memory-mapped special-function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfrs mapped at ff00h to ff1fh can be accessed with short direct addressing. [operand format] symbol description sfr special-function register name sfrp 16-bit manipulatable special-function register name (even addresses only) [example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 11110110 00100000 [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 84 chapter 3 cpu architecture user s manual u12790ej2v0ud 3.4.6 register indirect addressing [function] this addressing is used to address the memory to be manipulated by using the contents of the register pair specified by the register pair code in an instruction word as the operand address. the register pair specified is in the register bank specified by the register bank select flags (rbs0 and rbs1). this addressing can be used for the entire memory space. [operand format] symbol description [de], [hl] [example] mov a, [de]; when selecting [de] as register pair operation code 10000101 [illustration] 15 0 8 d 7 e 0 7 7 0 a de memory 85 chapter 3 cpu architecture user s manual u12790ej2v0ud 3.4.7 based addressing [function] this addressing mode is used to address a memory location specified by the result of adding the 8-bit immediate data to the contents of the hl register pair which is used as a base register. the hl register pair accessed is the register in the register bank specified by the register bank select flags (rbs0 and rbs1). addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be used for the entire memory space. [operand format] symbol description [hl + byte] [example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000 [illustration] hl 16 0 8 7 hl a 70 70 memory the contents of the addressed memory are transferred. +10 86 chapter 3 cpu architecture user s manual u12790ej2v0ud 3.4.8 based indexed addressing [function] this addressing mode is used to address a memory location specified by the result of adding the contents of the b or c register specified in the instruction word to the contents of the hl register pair which is used as a base register. the hl, b, and c registers accessed are the registers in the register bank specified by the register bank select flags (rbs0 and rbs1). addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be used for the entire memory space. [operand format] symbol description [hl + b], [hl + c] [example] in the case of mov a, [hl + b] operation code 10101011 [illustration] hl 16 0 8 7 hl a 70 70 memory 70 + b ? ? ? ? ? the contents of the addressed memory are transferred. 87 chapter 3 cpu architecture user s manual u12790ej2v0ud 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. stack addressing can be used to address the internal high-speed ram area only. [example] in the case of push de operation code 10110101 [illustration] fee0h fee0h fedfh fedeh d e fedeh sp sp 7 0 memory 88 user? manual u12790ej2v0ud chapter 4 port functions 4.1 port functions the pd178078 and 178098a subseries products incorporate eight input ports, eight output ports and 64 i/o ports. figure 4-1 shows the port configuration. every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. besides port functions, the ports can also serve as on-chip hardware i/o pins. figure 4-1. port types ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? port 5 port 0 ? ? ? ? ? ? ? ? ? port 1 ? ? ? ? ? ? ? ? ? port 2 ? ? ? ? ? ? ? ? ? port 3 ? ? ? ? ? ? ? ? ? port 4 ? ? ? ? ? ? ? ? ? port 6 ? ? ? ? ? ? ? ? ? ? ? ? port 7 ? ? ? ? ? ? ? ? ? port 13 ? ? ? ? ? port 12 port 10 p00 p07 p10 p17 p20 p27 p30 p37 p50 p57 p60 p67 p70 p77 p100 p102 p120 p124 p130 p137 p40 p47 89 chapter 4 port functions user s manual u12790ej2v0ud table 4-1. port functions (1/2) pin name i/o function after reset alternate function p00 to p07 i/o port 0. input intp0 to intp7 8-bit i/o port. can be set to input or output mode in 1-bit units. p10 to p17 input port 1. input ani0 to ani7 8-bit input port. p20 i/o port 2. input si1 p21 8-bit i/o port. so1 p22 can be set to input or output mode in 1-bit units. sck1 p23 stb p24 busy p25 si0/sb0/sda0 p26 so0/sb1/sda1 p27 sck0/scl p30 i/o port 3. input vm45 p31 8-bit i/o port. to0 p32 can be set to input or output mode in 1-bit units. ti00 p33 ti01 p34 ti50 p35 ti51 p36 beep0 p37 buz p40 to 47 i/o port 4. input 8-bit i/o port. can be set to input or output mode in 1-bit units. p50 to p57 i/o port 5. input 8-bit i/o port. can be set to input or output mode in 1-bit units. p60 to p67 i/o port 6. input 8-bit i/o port. can be set to input or output mode in 1-bit units. p70 i/o port 7. input si3 p71 8-bit i/o port. so3 p72 can be set to input or output mode in 1-bit units. sck3 p73 p74 rxd0 note 1 p75 txd0 note 1 p76, p77 90 chapter 4 port functions user s manual u12790ej2v0ud table 4-1. port functions (2/2) pin name i/o function after reset alternate function p100 i/o port 10. input p101 3-bit i/o port. amifc p102 can be set to input or output mode in 1-bit units. fmifc p120 i/o port 12. input tx0 note 2 p121 5-bit i/o port. rx0 note 2 p122 to p124 can be set to input or output mode in 1-bit units. p130 output port 13. to50 p131 8-bit output port. to51 p132 to p137 n-ch open-drain output port (12 v tolerant) notes 1 . pd178076, 178078, and 178f098 only. 2. pd178096a, 178098a, and 178f098 only. 91 chapter 4 port functions user s manual u12790ej2v0ud 4.2 port configuration a port consists of the following hardware. table 4-2. configuration of port item configuration control register port mode register (pmm: m = 0, 2 to 7, 10, 12) port total: 80 pins (8 input, 8 output, 64 i/o) 4.2.1 port 0 port 0 is an 8-bit i/o port with an output latch. the p00 to p07 pins can be set to input mode/output mode in 1- bit units using port mode register 0 (pm0). alternate functions include external interrupt request input. reset input sets port 0 to the input mode. figure 4-2 shows the block diagram of port 0. cautions 1. because port 0 also serves as an external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. when using the output mode, therefore, preset the interrupt mask flag to 1. 2. when the external interrupt request function is switched to the port function, edge detection may be performed. therefore, set bit n (egpn) of the external interrupt rising edge enable register (egp) and bit n (egnn) of the external interrupt falling edge enable register (egn) to 0 before selecting the port mode. remark n = 0 to 7 figure 4-2. block diagram of p00 to p07 pm: port mode register rd: port 0 read signal wr: port 0 write signal wr pm wr port rd p00/intp0 to p07/intp7 selector output latch (p00 to p07) pm00 to pm07 internal bus 92 chapter 4 port functions user s manual u12790ej2v0ud 4.2.2 port 1 port 1 is an 8-bit input port. alternate functions include a/d converter analog input. figure 4-3 shows the block diagram of port 1. figure 4-3. block diagram of p10 to p17 rd: port 1 read signal p10/ani0 to p17/ani7 rd internal bus 93 chapter 4 port functions user s manual u12790ej2v0ud 4.2.3 port 2 port 2 is an 8-bit i/o port with an output latch. the p20 to p27 pins can be set to input mode/output mode in 1- bit units using port mode register 2 (pm2). alternate functions include serial interface data i/o, clock i/o, automatic transmit/receive busy input, and strobe output. reset input sets port 2 to the input mode. figures 4-4 and 4-5 show the block diagrams of port 2. cautions 1. when using port 2 for the serial interface, set the input/output mode and output latch according to the function used. for the setting method, refer to table 4-3 port mode register and output latch settings when using alternate functions and figure 13-5 format of serial operating mode register 0 (csim0). 2. when reading the pin state in sbi mode, set pm2n to 1 (n = 5, 6) (refer to the description of (10) method used to judge busy state of a slave (e) in 13.4.3 sbi mode operation). figure 4-4. block diagram of p20 to p26 pm: port mode register rd: port 2 read signal wr: port 2 write signal wr pm wr port rd selector output latch (p20 to p26) pm20 to pm26 internal bus alternate function p20/si1, p21/so1, p22/sck1 p23/stb, p24/busy, p25/si0/sb0/sda0, p26/so0/sb1/sda1 94 chapter 4 port functions user s manual u12790ej2v0ud figure 4-5. block diagram of p27 pm: port mode register rd: port 2 read signal wr: port 2 write signal wr pm wr port rd selector output latch (p27) pm27 internal bus alternate function p27/sck0/scl 95 chapter 4 port functions user s manual u12790ej2v0ud 4.2.4 port 3 port 3 is an 8-bit i/o port with an output latch. the p30 to p37 pins can be set to input mode/output mode in 1-bit units using port mode register 3 (pm3). alternate functions include v dd = 4.5 v monitor output, timer output, timer input, and buzzer output. reset input sets port 3 to the input mode. figure 4-6 shows the block diagram of port 3. figure 4-6. block diagram of p30 to p37 pm: port mode register rd: port 3 read signal wr: port 3 write signal wr pm wr port rd selector output latch (p30 to p37) pm30 to pm37 internal bus alternate function p30/vm45, p31/to0, p32/ti00 p33/ti01, p34/ti50, p35/ti51, p36/beep0, p37/buz 96 chapter 4 port functions user s manual u12790ej2v0ud 4.2.5 port 4 port 4 is an 8-bit i/o port with an output latch. the p40 to p47 pins can be set to input mode/output mode in 8-bit units using port mode register 4 (pm4). reset input sets port 4 to the input mode. figure 4-7 shows the block diagram of port 4. figure 4-7. block diagram of p40 to p47 pm: port mode register rd: port 4 read signal wr: port 4 write signal wr mm wr port rd selector output latch (p40 to p47) pm40 to pm47 internal bus p40 to p47 97 chapter 4 port functions user s manual u12790ej2v0ud 4.2.6 port 5 port 5 is an 8-bit i/o port with an output latch. the p50 to p57 pins can be set to input mode/output mode in 1-bit units using port mode register 5 (pm5). reset input sets port 5 to the input mode. figure 4-8 shows the block diagram of port 5. figure 4-8. block diagram of p50 to p57 pm: port mode register rd: port 5 read signal wr: port 5 write signal wr pm wr port rd selector output latch (p50 to p57) pm50 to pm57 internal bus p50 to p57 98 chapter 4 port functions user s manual u12790ej2v0ud 4.2.7 port 6 port 6 is an 8-bit i/o port with an output latch. the p60 to p67 pins can be set to input mode/output mode in 1-bit units using port mode register 6 (pm6). reset input sets port 6 to the input mode. figure 4-9 shows the block diagram of port 6. figure 4-9. block diagram of p60 to p67 pm: port mode register rd: port 6 read signal wr: port 6 write signal wr pm wr port rd selector output latch (p60 to p67) pm60 to pm67 internal bus p60 to p67 99 chapter 4 port functions user s manual u12790ej2v0ud 4.2.8 port 7 port 7 is an 8-bit i/o port with an output latch. the p70 to p77 pins can be set to input mode/output mode in 1-bit units using port mode register 7 (pm7). alternate functions include serial interface data i/o, clock i/o, and asynchronous interface data i/o note . reset input sets port 7 to the input mode. figures 4-10 and 4-11 show the block diagrams of port 7. note pd178076, 178078, and 178f098 only figure 4-10. block diagram of p70 to p72, p74, and p75 pm: port mode register rd: port 7 read signal wr: port 7 write signal rd p70/si3 p71/so3 p72/sck3 p74/rxd0 p75/txd0 wr port wr pm output latch (p70 to p72, p74, p75) pm70 to pm72 pm74, pm75 selector alternate function internal bus 100 chapter 4 port functions user s manual u12790ej2v0ud figure 4-11. block diagram of p73, p76, and p77 pm: port mode register rd: port 7 read signal wr: port 7 write signal rd p73, p76, p77 wr port wr mm output latch (p73, p76, p77) pm73, pm76, pm77 selector internal bus 101 chapter 4 port functions user s manual u12790ej2v0ud 4.2.9 port 10 port 10 is a 3-bit i/o port with an output latch. the p100 to p102 pins can be set to input mode/output mode in 1-bit units using port mode register 10 (pm10). alternate functions include am intermediate frequency counter and fm intermediate frequency counter input. reset input sets port 10 to the input mode. figures 4-12 and 4-13 show the block diagrams of port 10. figure 4-12. block diagram of p100 pm: port mode register rd: port 10 read signal wr: port 10 write signal rd p100 wr port wr mm output latch (p100) pm100 selector internal bus 102 chapter 4 port functions user s manual u12790ej2v0ud figure 4-13. block diagram of p101 and p102 pm: port mode register rd: port 10 read signal wr: port 10 write signal internal bus rd p101/amifc p102/fmifc wr port wr mm output latch (p101, p102) pm101, pm102 selector 103 chapter 4 port functions user s manual u12790ej2v0ud 4.2.10 port 12 port 12 is a 5-bit i/o port with an output latch. the p120 to p124 pins can be set to input mode/output mode in 1-bit units using port mode register 12 (pm12). alternate functions include data i/o note of the iebus controller. reset input sets port 12 to the input mode. figures 4-14 and 4-15 show the block diagrams of port 12. note pd178096a, 178098a, and 178f098 only figure 4-14. block diagram of p120 and p121 pm: port mode register rd: port 12 read signal wr: port 12 write signal rd p120/tx0 p121/rx0 wr port wr pm output latch (p120, p121) pm120, pm121 selector alternate function internal bus 104 chapter 4 port functions user s manual u12790ej2v0ud figure 4-15. block diagram of p122 to p124 pm: port mode register rd: port 12 read signal wr: port 12 write signal wr pm wr port rd selector p122 to p124 output latch (p122 to p124) pm122 to pm124 internal bus 105 chapter 4 port functions user s manual u12790ej2v0ud 4.2.11 port 13 port 13 is an 8-bit n-ch open-drain output port with an output latch. alternate functions include timer output. reset input sets port 13 to the general-purpose output port mode. figure 4-16 shows the block diagram of port 13. figure 4-16. block diagram of p130 to p137 rd: port 13 read signal wr: port 13 write signal rd p130/to50 p131/to51 p132 to p137 wr port output latch (p130 to p137) internal bus alternate function 106 chapter 4 port functions user? manual u12790ej2v0ud 4.3 registers controlling port function ports are controlled by the corresponding port mode registers (pm0, pm2 to pm7, pm10, and pm12). these registers set the corresponding ports to the input or output mode in 1-bit units. these port mode registers can be set by using a 1-bit or 8-bit memory manipulation instruction. reset input sets the values of these registers to ffh. when using the alternate-function pins of each port, set the corresponding port mode register and output latch as shown in table 4-3. caution because port 0 also serves as an external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. when using the output mode, therefore, preset the interrupt mask flag to 1. remark the p10 to p17 pins are input-only pins and the p130 to p137 pins are output-only pins. 107 chapter 4 port functions user s manual u12790ej2v0ud table 4-3. port mode register and output latch settings when using alternate functions pin name alternate function pm p name i/o p00 to p07 intp0 to intp7 input 1 p20 si1 input 1 p21 so1 output 0 0 p22 sck1 input 1 output 0 0 p23 stb output 0 0 p24 busy input 1 p30 vm45 output 0 0 p31 to0 output 0 0 p32 ti00 input 1 p33 ti01 input 1 p34 ti50 input 1 p35 ti51 input 1 p36 beep0 output 0 0 p37 buz output 0 0 p70 si3 input 1 p71 so3 output 0 0 p72 sck3 input 1 output 0 0 p74 rxd0 input 1 p75 txd0 output 0 0 p101 amifc input 1 p102 fmifc input 1 p120 tx0 output 0 0 p121 rx0 input 1 p130 to50 output 0 p131 to51 output 0 cautions 1. when using the above alternate-function pins as output pins, be sure to set the output latch (p ) to 0. 2. when p25 to p27 are used for the serial interface, the input/output mode or output latch must be set according to the function used. for the setting method, refer to figure 13- 5 format of serial operating mode register 0 (csim0). remark : don t care pm : port mode register p : output latch of port 108 chapter 4 port functions user s manual u12790ej2v0ud figure 4-17. format of port mode registers pm0 pm7 pm2 pm07 pm06 pm03 pm02 pm01 1 76543210 symbol pm3 pm5 ff20h ff27h ff22h ff23h ff25h ffh ffh ffh ffh ffh r/w r/w r/w r/w r/w address after reset r/w pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 pm6 ff26h ffh r/w pm67 pm66 pm65 pm64 pm63 pm62 pm61 pm60 pm05 pm04 pm12 pmmn pmn pin input/output mode selection (m = 0, 2 to 7, 12 : n = 0 to 7) 0 1 output mode (output buffer on) input mode (output buffer off) ff2ch ffh r/w pm122 pm121 pm120 1 pm124 pm123 11 pm4 ff24h ffh r/w pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 pm10 ff2ah ffh r/w 11 111 pm102 pm101 pm100 109 chapter 4 port functions user? manual u12790ej2v0ud 4.4 port function operations port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is held until data is written to the output latch again. the data in the output latch is cleared after reset. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is held until data is written to the output latch again. 4.4.2 reading from i/o port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 4.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is held until data is written to the output latch again. the data in the output latch is cleared after reset. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, for a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 110 user? manual u12790ej2v0ud chapter 5 clock generator 5.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the system clock oscillator oscillates at frequencies of 6.3 mhz note . oscillation can be stopped by executing the stop instruction or setting the processor clock control register (pcc). note in addition to the 6.3 mhz crystal resonator, a 4.5 mhz crystal resonator can also be connected to the pd178078 and 178098a subseries. when using the system clock at a frequency of 4.5 mhz, set bit 0 (dtsck0) of the dts system clock select register (dtsck) to 1. set the dtsck0 flag after power application and reset by the reset pin, and before using the basic timer, buzzer output controller (beep0), pll frequency synthesizer, and frequency counter. when using the iebus controller of the pd178096a, 178098a, and 178f098, however, be sure to use the 6.3 mhz crystal resonator. at this time, it is not necessary to set the dtsck0 flag. the timing of the basic timer, buzzer output controller (beep0), pll frequency synthesizer, and frequency counter described in 8.3 operation of basic timer , 10.3.1 (1) beep frequency select register 0 (beepcl0) , 19.3 (2) pll reference mode register (pllrf) , and 20.3 (1) if counter mode select register (ifcmd) is not changed. figure 5-1. format of dts system clock select register (dtsck) dtsck0 system clock selection 0 6.3 mhz 1 4.5 mhz 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 dtsck0 symbol dtsck address ffaah after reset 00h r/w r/w 111 chapter 5 clock generator user s manual u12790ej2v0ud 5.2 clock generator configuration the clock generator consists of the following hardware. table 5-1. configuration of clock generator item configuration control registers processor clock control register (pcc) oscillation stabilization time select register (osts) oscillator system clock oscillator figure 5-2. block diagram of clock generator f x f x 2 f x 2 2 f x 2 3 f x 2 4 halt 3 3 osts2 osts1 osts0 pcc2 pcc1 pcc0 x1 x2 stop clock to other than peripheral hardware cpu clock (f cpu ) system clock oscillator prescaler prescaler standby controller wait controller selector internal bus internal bus processor clock control register (pcc) oscillation stabilization time select register (osts) 112 chapter 5 clock generator user s manual u12790ej2v0ud 5.3 clock generator control registers the clock generator is controlled by the following two registers. processor clock control register (pcc) oscillation stabilization time select register (osts) (1) processor clock control register (pcc) the clock generator is controlled by the processor clock control register (pcc). pcc sets the cpu clock. pcc is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pcc to 04h. figure 5-3. format of processor clock control register note bits 3 to 7 are read-only. remark f x : system clock oscillation frequency 000 0 pcc2 pcc1 pcc0 pcc fffbh 04h r/w note 76 54 symbol address after reset r/w 0 76 3 2 0 1 0 0 pcc2 cpu ciock (f cpu ) selection minimum instruction execution time: 2/f cpu f x = 6.3 mhz operation pcc1 pcc0 0 0 0 1 0 0 1 1 0 1 100 setting prohibited other than above r/w f x /2 f x /2 2 f x /2 3 f x /2 4 f x 0.64 s 1.27 s 2.54 s 5.08 s 0.32 s 113 chapter 5 clock generator user? manual u12790ej2v0ud (2) oscillation stabilization time select register (osts) this register is used to select the time required for oscillation to stabilize after the reset signal has been input or the stop mode has been released. this register is set by an 8-bit memory manipulation instruction. reset input set osts to 04h. it therefore takes 2 17 /f x to release the stop mode by reset input. figure 5-4. format of oscillation stabilization time select register (osts) osts2 osts1 osts0 oscillation stabilization time selection 0002 12 /f x (650 s) 0012 14 /f x (2.60 ms) 0102 15 /f x (5.20 ms) 0112 16 /f x (10.4 ms) 1002 17 /f x (20.8 ms) other than above setting prohibited remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 6.3 mhz address fffah symbol osts 7 0 6 0 5 0 4 0 3 0 2 osts2 1 osts1 0 osts0 after reset 04h r/w r/w 114 chapter 5 clock generator user? manual u12790ej2v0ud 5.4 system clock oscillator 5.4.1 system clock oscillator the system clock oscillator oscillates with a crystal resonator (6.3 mhz or 4.5 mhz) connected to the x1 and x2 pins. figure 5-5 shows an external circuit of the system clock oscillator. figure 5-5. external circuit of system clock oscillator crystal oscillation caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in figure 5-5 to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring to with other signal lines. do not route wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as gnd. do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. crystal resonator gnd0 x1 x2 115 chapter 5 clock generator user s manual u12790ej2v0ud 5.4.2 incorrect resonator connection figure 5-6 shows examples of incorrect resonator connection. figure 5-6. examples of incorrect connection resonator (1/2) (a) too long wiring (b) crossed signal line (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) x2 gnd0 x1 x2 gnd0 x1 portn (n = 0 to 7, 10, 12, 13) x2 gnd0 x1 x2 gnd0 x1 portn (n = 0 to 7, 10, 12, 13) v dd 0 abc high current high current 116 chapter 5 clock generator user s manual u12790ej2v0ud figure 5-6. examples of incorrect connection resonator (2/2) (e) signals are fetched 5.4.3 divider the divider divides the system clock oscillator output (f x ) and generates various clocks. x2 gnd0 x1 117 chapter 5 clock generator user s manual u12790ej2v0ud 5.5 clock generator operations the clock generator generates the following clocks and controls the cpu operating mode including the standby mode. system clock f x cpu clock f cpu clock to peripheral hardware the following clock generator functions and operations are determined by the processor clock control register (pcc). (a) upon generation of the reset signal, the lowest speed mode of the system clock (5.08 s when operated at 6.3 mhz) is selected (pcc = 04h). system clock oscillation stops while a low level is being applied to the reset pin. (b) one of the five minimum instruction execution times (0.317, 0.635, 1.27, 2.54, 5.08 s at 6.3 mhz) can be selected by setting pcc. (c) two standby modes, stop and halt, are available. (d) the system clock is divided and supplied to the peripheral hardware. the peripheral hardware also stops if the system clock is stopped. 118 chapter 5 clock generator user? manual u12790ej2v0ud table 5-2. maximum time required for cpu clock switchover pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 000001010011100 0 0 0 16 instructions 16 instructions 16 instructions 16 instructions 0 0 1 8 instructions 8 instructions 8 instructions 8 instructions 0 1 0 4 instructions 4 instructions 4 instructions 4 instructions 0 1 1 2 instructions 2 instructions 2 instructions 2 instructions 1 0 0 1 instruction 1 instruction 1 instruction 1 instruction set values after switchover set values before switchover remark one instruction is the minimum instruction execution time with the pre-switchover cpu clock. pcc2 pcc1 pcc0 5.6 changing system clock and cpu clock settings 5.6.1 time required for switchover between system clock and cpu clock the system clock and cpu clock can be switched over by setting bits 0 to 2 (pcc0 to pcc2) of the processor clock control register (pcc). the actual switchover operation is not performed directly after writing to the pcc; the operation continues on the pre-switchover clock for several instructions (refer to table 5-2). 119 user? manual u12790ej2v0ud chapter 6 16-bit timer/event counter 0 6.1 functions of 16-bit timer/event counter 0 16-bit timer/event counter 0 has the following functions. (1) interval timer 16-bit timer/event counter 0 generates interrupt requests at the preset time interval. number of counts: 2 to 65536 (2) external event counter 16-bit timer/event counter 0 can measure the number of pulses with a high-/low-level width in a signal input externally. valid level pulse width: 16/f x or more (3) pulse width measurement 16-bit timer/event counter 0 can measure the pulse width of an externally input signal. valid level pulse width: 2/f x or more (4) square-wave output 16-bit timer/event counter 0 can output a square wave with any selected frequency. cycle: (2 2 to 65536 2) count clock cycle (5) one-shot pulse output 16-bit timer/event counter 0 can output a one-shot pulse for which any output pulse width can be set. (6) ppg output 16-bit timer/event counter 0 can output a square wave that has an arbitrary cycle and pulse width. 2 < pulse width < cycle (ffff + 1) h figure 6-1 shows the block diagram. 120 chapter 6 16-bit timer/event counter 0 user? manual u12790ej2v0ud figure 6-1. block diagram of 16-bit timer/event counter 0 ti01/p33 f x /2 f x /2 2 f x /2 6 f x /2 3 ti00/p32 2 prm01 prm00 crc02 crc02 crc01 crc00 inttm00 to0/p31 inttm01 tmc03 tmc02 tmc01 ovf0 ospt ospe toc04 lvs0 lvr0 toc01 toe0 pm31 internal bus internal bus capture/compare control register 0 (crc0) noise eliminator noise eliminator noise eliminator match match 16-bit timer counter 0 (tm0) 16-bit capture/compare register 00 (cr00) selector selector clear output controller output latch (p31) prescaler mode register 0 (prm0) 16-bit timer mode control register 0 (tmc0) timer output control register 0 (toc0) 16-bit capture/compare register 01 (cr01) selector selector 121 chapter 6 16-bit timer/event counter 0 user? manual u12790ej2v0ud 6.2 configuration of 16-bit timer/event counter 0 16-bit timer/event counter 0 consists of the following hardware. table 6-1. configuration of 16-bit timer/event counter 0 item configuration timer counter 16-bit timer counter 0 (tm0) register 16-bit capture/compare registers 00 and 01 (cr00 and cr01) timer input ti00, ti01 timer output to0 control registers ?16-bit timer mode control register 0 (tmc0) capture/compare control register 0 (crc0) 16-bit timer output control register 0 (toc0) prescaler mode register 0 (prm0) port mode register 3 (pm3) port 3 (p3) (1) 16-bit timer counter 0 (tm0) tm0 is a 16-bit read-only register that counts count pulses. the count value is incremented at the rising edge of the count clock. if the count value is read while the register is operating, input of the count clock is temporarily stopped, and the count value at that point is read. the count value is reset to 0000h in the following cases. <1> when the reset signal is input <2> when tmc03 and tmc02 are cleared. <3> when the valid ti00 edge is input in the clear & start mode <4> when tm0 and cr00 match in the clear & start mode <5> when ospt is set or the valid ti00 edge is input in the one-shot pulse output mode (2) 16-bit capture/compare register 00 (cr00) cr00 is a 16-bit register with both the functions of a capture register and a compare register. whether this register is used as a capture register or a compare register is specified by bit 0 (crc00) of capture/compare control register 0. when cr00 is used as compare register the value set to cr00 is always compared with the count value of 16-bit timer counter 0 (tm0). when the two values match, an interrupt request (inttm00) is generated. when tm0 is used as an interval timer, cr00 is also used to hold the interval time. when cr00 is used as capture register the valid edge of the ti00/p32 pin or the ti01/p33 pin can be selected as the capture trigger. the valid edge of ti00 and ti01 is specified by prescaler mode register 0 (prm0) (refer to table 6-2). 122 chapter 6 16-bit timer/event counter 0 user? manual u12790ej2v0ud table 6-2. cr00 capture trigger and valid edges of ti00 and ti01 pins (1) ti00 pin valid edge selected as capture trigger (crc01 = 1, crc00 = 1) cr00 capture trigger ti00 pin valid edge es01 es00 falling edge rising edge 0 1 rising edge falling edge 0 0 no capture operation both rising and falling edges 1 1 (2) ti01 pin valid edge selected as capture trigger (crc01 = 0, crc00 = 1) cr00 capture trigger ti01 pin valid edge es11 es10 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. setting es01, es00 = 1, 0 and es11, es10 = 1, 0 is prohibited. 2. es01, es00: bits 5 and 4 of prescaler mode register 0 (prm0) es11, es10: bits 7 and 6 of prescaler mode register 0 (prm0) crc01, crc00: bits 1 and 0 of capture/compare control register 0 (crc0) cr00 is set by a 16-bit memory manipulation instruction. cr00 is undefined after reset. cautions 1. set cr00 to a value other than 0000h in the clear & start mode entered on a match between tm0 and cr00. however, in the free-running mode and in the clear mode using the valid edge of ti00, if cr00 is set to 0000h, an interrupt request (inttm00) is generated when cr00n changes from 0000h to 0001h following overflow (ffffh). 2. if the new value of cr00 is less than the value of 16-bit timer counter 0 (tm0), tm0 continues counting, overflows, and then starts counting from 0 again. if the new value of cr00 is less than the old value, therefore, the timer must be reset and restarted after the value of cr00 is changed. 3. cr00 does not generate an interrupt request if it is captured at the valid edge of the ti00 pin. 4. do not select the ti00 valid edge as the count clock when using ti00 as a capture trigger. (3) 16-bit capture/compare register 01 (cr01) this is a 16-bit register with both the functions of a capture register and a compare register. whether cr01 is used as a capture register or a compare register is specified by using bit 2 (crc02) of capture/compare control register 0. when cr01 is used as compare register the value set to cr01 is always compared with the count value of 16-bit timer counter 0 (tm0). when the two values match, an interrupt request (inttm01) is generated. 123 chapter 6 16-bit timer/event counter 0 user? manual u12790ej2v0ud when cr01 is used as capture register the valid edge of the ti00/p32 pin can be selected as the capture trigger. the valid edge of ti00/p32 is specified by using prescaler mode register 0 (prm0) (refer to table 6-3). table 6-3. cr01 capture trigger and valid edge of ti00 pin (crc02 = 1) cr01 capture trigger ti00 pin valid edge es01 es00 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. setting es01, es00 = 1, 0 is prohibited. 2. es01, es00: bits 5 and 4 of prescaler mode register 0 (prm0) crc02: bit 2 of capture/compare control register 0 (crc0) cr01 is set by using a 16-bit memory manipulation instruction. cr01 is undefined after reset. cautions 1. set cr01 to a value other than 0000h in the clear & start mode entered on a match between tm0 and cr00. however, in the free-running mode and in the clear mode using the valid edge of ti00, if cr01 is set to 0000h, an interrupt request (inttm01) is generated when cr01 changes from 0000h to 0001h following overflow (ffffh). 2. when using cr01 as a capture register, do not select the ti00 valid edge as the count clock. 124 chapter 6 16-bit timer/event counter 0 user? manual u12790ej2v0ud 6.3 registers controlling 16-bit timer/event counter 0 the following six registers control 16-bit timer/event counter 0. 16-bit timer mode control register 0 (tmc0) capture/compare control register 0 (crc0) 16-bit timer output control register 0 (toc0) prescaler mode register 0 (prm0) port mode register 3 (pm3) port 3 (p3) (1) 16-bit timer mode control register 0 (tmc0) this register specifies the operating mode of the 16-bit timer, clear mode of 16-bit timer counter 0 (tm0), and output timing, and detects an overflow. tmc0 is set by a 1-bit or 8-bit memory manipulation instruction. the value of this register is cleared to 00h after reset. caution 16-bit timer counter 0 (tm0) starts operating when tmc02 and tmc03 are set to values other than 0, 0 (operation stop mode). to stop operation, reset tmc02 and tmc03 to 0, 0. 125 chapter 6 16-bit timer/event counter 0 user? manual u12790ej2v0ud figure 6-2. format of 16-bit timer mode control register 0 (tmc0) tmc03 tmc02 tmc01 selection of operating mode selection of to0 output generation of interrupt and clear mode timing request 0 0 0 operation stops not affected not generated 001 (tm0 is cleared to 0). 0 1 0 free-running mode match between tm0 generated on match and cr00 or cr01 between tm0 and cr00 or 0 1 1 match between tm0 cr01 and cr00 or cr01, or valid edge of ti00 1 0 0 clear & start at valid edge match between tm0 of ti00 and cr00 or cr01 1 0 1 match between tm0 and cr00 or cr01, or valid edge of ti00 1 1 0 clear & start on match between tm0 match between tm0 and cr00 or cr01 111 and cr00 match between tm0 and cr00 or cr01, or valid edge of ti00 ovf0 detection of overflow of 16-bit timer counter 0 0 overflow 1 no overflow cautions 1. write the bits other than the ovf0 flag after stopping the timer operation. 2. the valid edge of the ti00/p32 pin is selected by prescaler mode register 0 (prm0). 3. if a mode in which tm0 is cleared and started on a match between tm0 and cr00 is selected, and if the value of tm0 changes from ffffh to 0000h with cr00 set to ffffh, the ovf0 flag is set to 1. remark to0: output pin of 16-bit timer/event counter 0 ti00: input pin of 16-bit timer/event counter 0 tm0: 16-bit timer counter 0 cr00: 16-bit capture/compare register 00 cr01: 16-bit capture/compare register 01 7 0 6 0 5 0 4 0 3 tmc03 2 tmc02 1 tmc01 <0> ovf0 symbol tmc0 address ff78h after reset 00h r/w r/w 126 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud (2) capture/compare control register 0 (crc0) this register controls the operations of the 16-bit capture/compare registers (cr00 and cr01). crc0 is set by using a 1-bit or 8-bit memory manipulation instruction. this register is cleared to 00h after reset. figure 6-3. format of capture/compare control register 0 (crc0) crc02 selection of operating mode of cr01 0 compare register 1 capture register crc01 selection of capture trigger of cr00 0 captured at valid edge of ti01 1 captured at reverse edge to valid edge of ti00 note crc00 selection of operating mode of cr00 0 compare register 1 capture register note if both the rising and falling edges are selected as the valid edges of ti00, cr00 does not perform a capture operation. cautions 1. be sure to set crc0 after stopping the timer operation. 2. do not specify cr00 as a capture register when a mode in which tm0 is cleared and started on a match between tm0 and cr00 is selected by 16-bit timer mode control register 0 (tmc0). 7 0 6 0 5 0 4 0 3 0 2 crc02 1 crc01 0 crc00 symbol crc0 address ff7ch after reset 00h r/w r/w 127 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud (3) 16-bit timer output control register 0 (toc0) this register controls the operation of the 16-bit timer/event counter output controller. it sets/resets the r- s flip-flop (lv0); enables/disables output inversion, timer output of 16-bit timer/event counter 0, and the one- shot pulse output operation; and sets the output trigger of the one-shot pulse. toc0 is set by a 1-bit or 8-bit memory manipulation instruction. the value of this register is cleared to 00h after reset. figure 6-4 shows the format of toc0. figure 6-4. format of 16-bit timer output control register 0 (toc0) ospt control of output trigger of one-shot pulse by software 0 no one-shot pulse trigger 1 one-shot pulse trigger ospe control of one-shot pulse output operation 0 successive pulse output 1 one-shot pulse output note toc04 control of timer output f/f on match between cr01 and tm0 0 inversion operation disabled 1 inversion operation enabled lvs0 lvr0 setting of timer output f/f status of 16-bit timer/event counter 0 0 0 not affected 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc01 control of timer output f/f on match between cr00 and tm0 0 inversion disabled 1 inversion enabled toe0 control of output of 16-bit timer/event counter 0 0 output disabled (output is fixed to 0 level) 1 output enabled note one-shot pulse output operates normally only in the free-running mode and the mode in which tm0 is cleared and started at the valid edge of ti00. cautions 1. be sure to set toc0 after stopping the timer. 2. lvs0 and lvr0 are 0 when they are read. 3. ospt is always 0 when read because it is automatically cleared after data has been set. 7 <6> <5> 4 <3> 0 ospt ospe lvr0 toc01 toe0 toc04 lvs0 <2> 1 <0> symbol toc0 address ff7eh after reset 00h r/w r/w 128 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud (4) prescaler mode register 0 (prm0) this register selects the count clock of 16-bit timer counter 0 (tm0) and the valid edges of the ti00 and ti01 input pins. prm0 is set by an 8-bit memory manipulation instruction. the value of this register is cleared to 00h after reset. figure 6-5. format of prescaler mode register 0 (prm0) es11 es10 selection of valid edge of ti01 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges es01 es00 selection of valid edge of ti00 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges prm01 prm00 selection of count clock 00f x /2 (3.15 mhz) 01f x /2 2 (1.58 mhz) 10f x /2 6 (98.4 khz) 1 1 valid edge of ti00 cautions 1. be sure to set data to prm0 after stopping the timer operation. 2. when the valid edge of ti00 is set as the count clock, do not set the mode in which tm0 is cleared and started at the valid edge of ti00, and do not set t100 as the capture trigger. 3. the capture trigger must be a pulse wider than two pulses of the selected count clock to ensure capturing. similarly, the external clock must have a pulse wider than two internal clocks (f x /2 3 ). 4. if the ti00 pin or ti01 pin goes high immediately after system reset, the rising edge is detected immediately after tm0 has been enabled to operate. keep this in mind when the pin is pulled up. however, when tm0 is enabled to operate again after it has been stopped, the rising edge is not detected. remarks 1. f x : system clock oscillation frequency 2. ti00, ti01: input pins of 16-bit timer/event counter 0 3. ( ): f x = 6.3 mhz 76543 es11 es10 es01 0 prm01 rpm00 es00 0 210 symbol prm0 address ff7ah after reset 00h r/w r/w 129 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud (5) port mode register 3 (pm3) this register sets port 3 i/o in 1-bit units. when using the p31/to0 pin for timer output, set pm31 and the output latch of p31 to 0. when using the p32/ti00 pin as a timer input (ti00), set pm32 to 1. when using the p33/ti01 pin as a timer input (ti01), set pm33 to 1. pm3 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 6-6. format of port mode register 3 (pm3) pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 76543210 symbol pm3 ff23h ffh r/w address after reset r/w pm3n selection of p3n pin i/o mode (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 130 chapter 6 16-bit timer/event counter 0 user? manual u12790ej2v0ud 6.4 operation of 16-bit timer/event counter 0 6.4.1 operation as interval timer 16-bit timer/event counter 0 operates as an interval timer when 16-bit timer mode control register 0 (tmc0) and capture/compare control register 0 (crc0) are set as shown in figure 6-7. an interrupt request is repeatedly generated at intervals specified by the count value preset to 16-bit capture/compare register 00 (cr00). when the count value of 16-bit timer counter 0 (tm0) matches the set value of cr00, the value of tm0 is cleared to 0 and an interrupt request signal (inttm00) is generated. the count clock of 16-bit timer/event counter 0 is selected by bits 0 and 1 (prm00 and prm01) of prescaler mode register 0 (prm0). for details of the operation when the value of the compare register is changed during timer count operation, refer to (3) in 6.6 notes on 16-bit timer/event counter 0 . figure 6-7. setting of control registers for interval timer operation (a) 16-bit timer mode control register 0 (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: when these bits are set to 1 or reset to 0, other functions can be used at the same time as the interval timer function. for details, refer to figures 6-2 and 6-3. 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clear & start on match between tm0 and cr00 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 is used as compare register. 131 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud figure 6-8. configuration of interval timer note ovf0 is 1 only when cr00 = ffffh in the interval timer. figure 6-9. timing of interval timer operation 16-bit capture/compare register 00 (cr00) 16-bit timer counter 0 (tm0) ovf0 note clear circuit inttm00 selector f x /2 f x /2 2 f x /2 6 ti00/p32 noise eliminator f x /2 3 count clock tm0 count value cr00 inttm00 to0 count start clear clear nn nn interval time interval time interrupt request acknowledged interrupt request acknowledged interval time t 0000h 0001h n 0000h 0001h n 0000h 0001h n remark interval time = (n + 1) t n = 0001h to ffffh 132 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud 6.4.2 operation as external event counter the external event counter counts the number of external clock pulses input to the ti00/p32 pin by using 16-bit timer counter 0 (tm0). each time the valid edge specified by prescaler mode register 0 (prm0) has been input to ti00/p32, the value of tm0 is incremented. when the count value of tm0 matches the value of capture/compare register 00 (cr00), tm0 is cleared to 0 and an interrupt request signal (inttm00) is generated. set cr00 to a value other than 0000h (one pulse cannot be counted). the rising, falling, or both rising and falling edges can be selected as the valid edge of ti00/p32 by using bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). because the operation is performed only after the valid level of the ti00 pin is detected twice by sampling using the internal clock (f x /2 3 ), noise with a short pulse width can be eliminated. figure 6-10. setting of control registers in external event counter mode (a) 16-bit timer mode control register 0 (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used at the same time as the external event counter function. for details, refer to figures 6-2 and 6-3. 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 is used as compare register. 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clear & start on match between tm0 and cr00. 133 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud figure 6-11. configuration of external event counter note ovf0 is 1 only when cr00 = ffffh in the external event counter. 16-bit timer counter 0 (tm0) 16-bit capture/compare register 00 (cr00) clear ovf0 note inttm00 internal bus noise elimi- nator f x /2 3 valid edge of ti00 match ti00 pin input (after noise eliminated) tm0 count value 0000h 0001h 0002h 0003h 0004h 0005h 0000h 0001h 0002h 0003h n n ? 1 n cr00 inttm00 figure 6-12. timing of external event counter (with rising edge specified) caution read tm0 to read the count value of the external event counter. 134 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud 6.4.3 pulse width measurement 16-bit timer counter 0 can be used to measure the pulse width of the signal input to the ti00/p32 and ti01/p33 pins. the pulse width can be measured by operating tm0 in the free-running mode, or by restarting the timer in synchronization with the edge of the signal input to the ti00/p32 pin. (1) pulse width measurement with free-running counter and one capture register when 16-bit timer counter 0 (tm0) operates in the free-running mode (refer to the register setting in figure 6-13) and if the edge specified by prescaler mode register 0 (prm0) is input to the ti00/p32 pin, the value of tm0 is loaded to 16-bit capture/compare register 01 (cr01) and an external interrupt request signal (inttm01) is set. the rising, falling, or both the rising and falling edges can be selected as the edge by using bits 6 and 7 (es10 and es11) of prm0. because the value of tm0 is captured only after the valid level of the ti00 pin is detected twice by sampling using the count clock cycle selected by prm0, noise with a short pulse width can be eliminated. figure 6-13. setting of control registers for pulse width measurement with free-running counter and one capture register (a) 16-bit timer mode control register 0 (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: when these bits are set to 1 or reset to 0, other functions can be used at the same time as the pulse width measurement function. for details, refer to figures 6-2 and 6-3. 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free-running mode 00000 crc02 1 crc01 0/1 crc00 0 crc0 cr00 is used as compare register. cr01 is used as capture register. 135 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud figure 6-14. configuration of pulse width measurement circuit with free-running counter figure 6-15. timing of pulse width measurement with free-running counter and one capture register (with both rising and falling edges specified) 16-bit capture/compare register 01 (cr01) 16-bit timer counter 0 (tm0) ovf0 inttm01 f x /2 f x /2 2 f x /2 6 ti00/p32 internal bus selector noise elimi- nator note clear ovf0 by software. count clock t tm0 count value 0000h d0 ? 1 0000h ffffh d2 d0 d1 d2 note ti00 (after noise eliminated) value loaded to cr01 inttm01 d0 d2 ? 1 ovf0 (d1 ? d0) t (10000h ? d1 + d2) t d0 ? 2 ti00 pin input d1 ? 1 d1 d0 + 1 d2 + 1 d1 + 1 136 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud (2) measurement of two pulse widths with free-running counter when 16-bit timer counter 0 (tm0) operates in the free-running mode (refer to figure 6-16), the pulse widths of the two signals input to the ti00/p32 and ti01/p33 pins can be simultaneously measured. when the edge specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0) is input to the ti00/p32 pin, the value of tm0 is captured to 16-bit capture/compare register 01 (cr01), and an external interrupt request signal (inttm01) is set. when the edge specified by bits 6 and 7 (es10 and es11) of prm0 is input to the ti01/p33 pin, the value of tm0 is captured to 16-bit capture/compare register 00 (cr00), and an external interrupt request signal (inttm00) is set. the edges of the ti00/p32 and ti01/p33 pins are specified by bits 4 and 5 (es00 and es01), and bits 6 and 7 (es10 and es11) of prm0, respectively. the rising, falling, or both the rising and falling edges can be specified. because the value of tm0 is captured only after the valid level of the ti00 pin is detected twice by sampling using the count clock cycle selected by prescaler mode register 0 (prm0), noise with a short pulse width can be eliminated. figure 6-16. setting of control registers for measurement of two pulse widths with free-running counter (a) 16-bit timer mode control register 0 (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: when these bits are set to 1 or reset to 0, other functions can be used at the same time as the pulse width measurement function. for details, refer to figures 6-2 and 6-3. 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free-running mode 00000 crc02 1 crc01 0 crc00 1 crc0 cr00 is used as capture register. value of tm0 is captured to cr00 at valid edge of ti01/p33 pin. cr01 is used as capture register. 137 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud about capture operation (free-running mode) the following charts show the operation of the capture register when the capture trigger is input. figure 6-17. capture operation of cr01 when rising edge is specified figure 6-18. timing of pulse width measurement by free-running counter (with both rising and falling edges specified) count clock tm0 ti00 rising edge detected cr01 inttm01 n 3n 2n 1 n n + 1 n count clock t tm0 count value 0000h 0001h d0 + 1 0000h ffffh d2 d2 + 1 d2 + 2 d0 d1 d1 d2 ti00 pin input (after noise eliminated) value loaded to cr01 inttm01 ti01 pin input value loaded to cr00 inttm00 ovf0 (d1 ? d0) t (10000h ? d1 + d2) t (10000h ? d1 + (d2 + 1)) t (d3 ? d2) t d0 d3 d2 + 1 note d1 + 1 d1 note clear ovf0 by software. 138 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud (3) pulse width measurement with free-running counter and two capture registers when 16-bit timer counter 0 (tm0) operates in the free-running mode (refer to figure 6-19), the pulse widths of the signals input to the ti00/p32 pin can be measured. when the edge specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0) is input to the ti00/p32 pin, the value of tm0 is captured to 16-bit capture/compare register 01 (cr01), and an external interrupt request signal (inttm01) is set. the value of tm0 is also captured to 16-bit capture/compare register 00 (cr00) when the reverse edge to the edge that triggers capturing to the cr01 is input to the pin. the edge of the ti00/p32 pin is specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). the rising or falling edge can be specified. because the value of tm0 is captured only after the valid level of the ti00 pin is detected twice by sampling using the count clock cycle selected by prescaler mode register 0 (prm0), noise with a short pulse width can be eliminated. caution when both the rising and falling edges are specified as the valid edges of the ti00/p32 pin, 16-bit capture/compare register 00 (cr00) cannot perform a capture operation. figure 6-19. setting of control registers for measurement with free- running counter and two capture registers (a) 16-bit timer mode control register 0 (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: when these bits are set to 1 or reset to 0, other functions can be used at the same time as the pulse width measurement function. for details, refer to the descriptions of each control register. 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free-running mode 00000 crc02 1 crc01 1 crc00 1 crc0 cr00 is used as capture register. value of tm0 is captured to cr00 at reverse edge to valid edge of ti00/p32 pin. cr01 is used as capture register. 139 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud figure 6-20. timing of pulse width measurement with free-running counter and two capture registers (with rising edge specified) note clear ovf0 by software. (4) pulse width measurement by restarting when the valid edge of the ti00/p32 pin is detected, the pulse width of the signal input to the ti00/p32 pin can be measured by clearing 16-bit timer counter 0 (tm0) and restarting counting after the count value of tm0 is captured to 16-bit capture/compare register 01 (cr01) (refer to figure 6-22). the rising or falling edge can be specified as the valid edge by using bit 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). because the value of tm0 is captured only after the valid level of the ti00 pin is detected twice by sampling using the count clock cycle selected by prescaler mode register 0 (prm0), noise with a short pulse width can be eliminated. caution when both the rising and falling edges are specified as the valid edges of the ti00/p32 pin, 16-bit capture/compare register 00 (cr00) cannot perform a capture operation. count clock t tm0 count value 0000h 0001h d0 + 1 0000h ffffh d2 d0 d2 ti00 pin input (after noise eliminated) value loaded to cr01 inttm01 d0 d3 d1 + 1 d2 + 1 d1 ovf0 (d1 ? d0) t (10000h ? d1 + d2) t (d3 ? d2) t d1 d3 note value loaded to cr00 140 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud figure 6-21. setting of control registers for pulse measurement by restarting (a) 16-bit timer mode control register 0 (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: when these bits are set to 1 or reset to 0, other functions can be used at the same time as the pulse width measurement function. for details, refer to figures 6-2 and 6-3. figure 6-22. timing of pulse width measurement by restarting (with rising edge specified) count clock t tm0 count value 0000h 0001h 0000h 0001h 0001h 0000h d0 d2 ti00 pin input (after noise eliminated) value loaded to cr01 inttm01 d0 d1 d2 d1 t d2 t d1 value loaded to cr00 0000 tmc03 1 tmc02 0 tmc01 0/1 ovf0 0 tmc0 clears & start at valid edge of ti00/p32 pin 00000 crc02 1 crc01 1 crc00 1 crc0 cr00 is used as capture register. value of tm0 is captured to cr00 at reverse edge to valid edge of ti00/p32 pin. cr01 is used as capture register. 141 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud 6.4.4 square wave output operation the 16-bit timer/event counter can be used to output a square wave of any frequency at intervals specified by the count value preset to 16-bit capture/compare register 00 (cr00). when bits 0 (toe0) and 1 (toc01) of 16-bit timer output control register 0 (toc0) are set to 1, the output status of the to0 pin is inverted at the intervals specified by the count value preset to cr00. in this way, a square wave of any frequency can be output. figure 6-23. setting of control register in square wave output mode (a) 16-bit timer mode control register 0 (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register 0 (toc0) remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used at the same time as the square wave output function. for details, refer to figures 6-2, 6-3, and 6-4. 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 is used as compare register. 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clear & start on match between tm0 and cr00 0 ospt 0 ospe 0 toc04 0 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 toc output enabled output inverted on match between tm0 and cr00 specification of initial value of to0 output f/f output not inverted on match between tm0 and cr01 one-shot pulse output disabled 142 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud figure 6-24. timing of square wave output operation 6.4.5 one-shot pulse output operation the 16-bit timer/event counter can be used to output a one-shot pulse in synchronization with a software trigger or external trigger (ti00/p32 pin input). (1) one-shot pulse output with software trigger a one-shot pulse can be output to the to0/p31 pin by setting 16-bit timer mode control register 0 (tmc0), capture/compare control register 0 (crc0), and 16-bit timer output control register 0 (toc0) as shown in figure 6-25, and setting bit 6 (ospt) of toc0 to 1 by software. when ospt is set to 1, 16-bit timer counter 0 (tm0) is cleared and started, and the output to ti00/p32 becomes active at the count value preset to 16-bit capture/compare register 01 (cr01). after that, the output becomes inactive at the count value preset to 16-bit capture/compare register 00 (cr00). after outputting the one-shot pulse, tm0 continues operating. to stop tm0, set tm0 to 00h. caution do not set ospt to 1 while the one-shot pulse is being output. to output the one-shot pulse again, wait until the inttm00 interrupt , which occurs on a match between tm0 and cr00, has occurred. count clock tm0 count value 0000h 0001h 0002h 0000h 0001h 0002h n ? 1n 0000h n ? 1n n cr00 inttm00 to0 pin output 143 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud figure 6-25. setting of control registers for one-shot pulse output operation with software trigger (a) 16-bit timer mode control register 0 (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register 0 (toc0) caution set cr00 and cr01 to a value in the following range. 0000h < cr01 < cr00 ffffh remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used at the same time as the one-shot pulse output function. for details, refer to figures 6-2, 6-3, and 6-4. 00000 crc02 0 crc01 0/1 crc00 0 crc0 cr00 is used as compare register. cr01 is used as compare register. 0 ospt 0 ospe 1 toc04 1 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 to0 output enabled output inverted on match between tm0 and cr00 specification of initial value of to0 output f/f output inverted on match between tm0 and cr01 specification of one-shot pulse output mode set to 1 to output one-shot pulse. 0000 tmc03 0/1 tmc02 0/1 tmc01 0/1 ovf0 0 tmc0 clear & start at valid edge of ti00/p32 pin, or free-running mode 144 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud figure 6-26. timing of one-shot pulse output operation with software trigger caution 16-bit timer counter 0 (tm0) starts operating as soon as tmc02 and tmc03 are set to values other than 0, 0 (operation stop mode). remark n < m (2) one-shot pulse output with external trigger a one-shot pulse can be output to the to0/p31 pin by using the valid edge of the ti00/p32 pin as an external trigger when 16-bit timer mode control register 0 (tmc0), capture/compare control register 0 (crc0), and 16- bit timer output control register 0 (toc0) are set as shown in figure 6-27. the rising, falling, or both the rising and falling edges can be selected as the valid edge of the ti00/p32 pin by bit 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). at the valid edge of the ti00/p32 pin, 16-bit timer counter 0 (tm0) is cleared and started, and the output to to0/p31 becomes active at the count value written in advance to 16-bit capture/compare register 01 (cr01). after that, the output becomes inactive at the count value written in advance in 16-bit capture/compare register 00 (cr00) note . note the case where n < m is described here. when n > m, the output becomes active with the cr00 register and inactive with the cr01 register. caution the external trigger is ignored even if generated while the one-shot pulse is being output. count clock tm0 count value cr01 set value cr00 set value inttm01 ospt inttm00 to0 pin output 0000 0001 n n + 1 0000 n 1 n m 1 m m + 1 0000 n m n m n m n m set 0ch to tmc0 (tm0 count start) one-shot pulse 145 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud figure 6-27. setting of control registers for one-shot pulse output operation with external trigger (a) 16-bit timer mode control register 0 (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register 0 (toc0) caution set cr00 and cr01 to a value in the following range. 0000h < cr01 < cr00 ffffh remark 0/1: when these bits are reset to 0 or set to 1, other functions can be used at the same time as the one-shot pulse output function. for details, refer to figures 6-2, 6-3, and 6-4. 00000 crc02 0 crc01 0/1 crc00 0 crc0 cr00 is used as compare register. cr01 is used as compare register. 0 ospt 0 ospe 1 toc04 1 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 to0 output enabled output inverted on match between tm0 and cr00 specification of initial value of to0 output f/f output inverted on match between tm0 and cr01 specification of one-shot pulse output mode 0000 tmc03 0/1 tmc02 0/1 tmc01 0/1 ovf0 0 tmc0 clear & start at valid edge of ti00/p32 pin, or free-running mode 146 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud figure 6-28. timing of one-shot pulse output operation with external trigger (clear & start at valid edge of ti00 with rising edge specified) caution 16-bit timer counter 0 (tm0) starts operating as soon as tmc02 and tmc03 are set to values other than 0, 0 (operation stop mode). remark n < m count clock tm0 count value cr01 set value cr00 set value inttm01 ti00 pin input inttm00 to0 pin output 0000 0001 0000 n n + 1 n + 2 m 2m 1 m m + 1 m + 2 m + 3 n m n m n m n m set 08h to tmc0 (tm0 count start) 147 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud 6.4.6 ppg output operation 16-bit timer/event counter 0 operates as a ppg (programmable pulse generator) output when 16-bit timer mode control register 0 (tmc0) and capture/compare control register 0 (crc0) are set as shown in figure 6-29. the ppg output pulse is a square wave and is output from the to0/p31 pin. one cycle of this pulse is specified by the count value preset to 16-bit capture/compare register 00 (cr00), and the pulse width is specified by the count value preset to 16-bit capture/compare register 01 (cr01). figure 6-29. setting of control register for ppg output operation (a) 16-bit timer mode control register 0 (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register 0 (toc0) cautions 1. set cr00 and cr01 to a value in the following range. 0000h < cr01 < cr00 ffffh 2. the cycle of the pulse generated by ppg output is (set value of cr00 + 1), and the duty factor is (set value of cr01 + 1)/(set value of cr00 + 1). remark : don t care 00000 crc02 0 crc01 crc00 0 crc0 cr00 is used as compare register. cr01 is used as compare register. 0000 tmc03 1 tmc02 1 tmc01 0 ovf0 0 tmc0 clear & start on match between tm0 and cr00 0 ospt 0 ospe 0 toc04 1 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 toc output enabled output inverted on match between tm0 and cr00 specification of initial value of to0 output f/f output inverted on match between tm0 and cr01 one-shot pulse output disabled 148 chapter 6 16-bit timer/event counter 0 user? manual u12790ej2v0ud figure 6-30. configuration of ppg output figure 6-31. ppg output operation timing remark 0000h < m < n ffffh t 0000h 0000h 0001h 0001h m ? 1 count clock tm0 count value to0 pulse width: (m + 1) t 1 cycle: (n + 1) t n cr00 capture value cr01 capture value m m n ? 1 n clear count start 16-bit capture/compare register 00 (cr00) 16-bit timer counter 0 (tm0) clear circuit selector f x /2 f x /2 2 f x /2 6 16-bit capture/compare register 01 (cr01) output controller to0/p31 ti00/p32 noise eliminator 149 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud 6.5 program list caution the following sample program is shown as an example to describe the operation of semiconductor products and their applications. therefore, when applying the following information to your devices, design the devices after performing evaluation on your own responsibility. 150 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud 6.5.1 interval timer /*******************************************************************************/ /* */ /* setting example of timer 0 interval timer mode */ /* cycle set to 98 as intervaltm0 (at 6.3 mhz for 1 ms) */ /* variable ppgdata prepared as rewrite data area */ /* : cycle (if 0000, no change) */ /* ppgdata to be checked at every inttm00, and changed if required. */ /* therefore, if change is required, set the change data in ppgdata. */ /* when changed, ppgdata cleared to 0000. */ /* */ /*******************************************************************************/ #pragma sfr #pragma ei #pragma di #define intervaltm0 98 /* cycle data to be set to cr00 */ #pragma interrupt inttm00 intervalint rb2 unsigned int ppgdata; /* data area to be set to timer 0 */ void main(void) { pcc = 0x0; /* set high-speed operation mode */ ppgdata = 0; /* set port */ /* set the following to output */ p3 = 0b11111101; /* clear p31 */ pm3.1 = 0; /* set p31 as output */ /* set interrupt */ tmmk00 = 0; /* cancel inttm00 interrupt mask */ /* set timer 0 */ prm0 = 0b00000010; /* count clock is fx/2^6 */ crc0 = 0b00000000; /* set cr00 and cr01 to compare register */ cr00 = intervaltm0; /* set cycle initial value to cr00 */ toc0 = 0b00000111; /* invert on match with cr00, initial value l */ tmc0 = 0b00001100; /* clear & start on match between tm0 and cr00 */ ei(); while(1); /* loop as dummy here */ } /* timer 0 interrupt function */ void intervalint() { unsigned int work; /***************************************************/ /* */ /* define variables required for interrupt here */ /* */ /***************************************************/ work = ppgdata; if (work != 0) { cr00 = work; ppgdata = 0; if (work == 0xffff) { tmc0 = 0b00000000; /* stop timer */ } } /***********************************************************/ /* */ /* describe processing required for interrupt below */ /* */ /***********************************************************/ } 151 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud 6.5.2 pulse width measurement by free-running counter and one capture register /******************************************************************************/ /* */ /* timer 0 operation sample */ /* pulse width measurement example by free-running and cr01 */ /* measurement results up to 16 bits and not checked for errors */ /* data[0]: end flag */ /* data[1]: measurement results (pulse width) */ /* data[2]: previous read value */ /* */ /******************************************************************************/ #pragma sfr #pragma ei #pragma di #pragma interrupt inttm01 intervalint rb2 unsigned int data[3]; /* data area */ void main(void) { unsigned int length; pcc = 0x0; /* set high-speed operation mode */ data[0] = 0; data[1] = 0; data[2] = 0; /* set port */ pm3.2 = 1; /* set p32 as input */ /* set interrupt */ tmmk01 = 0; /* cancel inttm01 interrupt mask */ /* set timer 0 */ prm0 = 0b00110010; /* both rising and falling edges for ti00 */ /* count clock is fx/2^6 */ crc0 = 0b00000100; /* set cr01 to capture register */ tmc0 = 0b00000100; /* start in free-run mode */ ei(); while(1){ /* dummy loop */ while(data[0] == 0); /* wait for measurement completion */ di(); /* prohibit interrupt for exclusive operation */ length = data[1]; /* read measurement results */ data[0] = 0; /* clear end flag */ ei(); /* exclusive operation completed */ } } /* timer 0 interrupt function */ void intervalint() { unsigned int work; /*****************************************************/ /* */ /* define variables required for interrupt here */ /* */ /*****************************************************/ work = cr01; /* read capture value */ data[1] = work - data[2]; /* calculate and update interval */ data[2] = work; /* update read value */ data[0] = 0xffff; /* set measurement completion flag*/ /***********************************************************/ /* */ /* describe processing required for interrupt below */ /* */ /***********************************************************/ } 152 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud 6.5.3 two-pulse-width measurement by free-running counter /******************************************************************************/ /* */ /* timer 0 operation sample */ /* two-pulse-width measurement sample by free-running */ /* measurement results up to 16 bits and not checked for errors */ /* result area at ti00 side */ /* data[0]: end flag */ /* data[1]: measurement results (pulse width) */ /* data[2]: previous read value */ /* result area at ti01 side */ /* data[3]: end flag */ /* data[4]: measurement results (pulse width) */ /* data[5]: previous read value */ /* */ /******************************************************************************/ #pragma sfr #pragma ei #pragma di #pragma interrupt inttm00 intervalint rb2 #pragma interrupt inttm01 intervalint2 rb2 unsigned int data[6]; /* data area */ void main(void) { unsigned int length,length2; pcc = 0x0; /* set high-speed operation mode */ data[0] = 0; /* clear data area */ data[1] = 0; data[2] = 0; data[3] = 0; data[4] = 0; data[5] = 0; /* set port */ pm3.2 = 1; /* set p32 as input */ pm3.3 = 1; /* set p33 as input */ /* set interrupt */ tmmk01 = 0; /* cancel inttm01 interrupt mask */ tmmk00 = 0; /* cancel inttm00 interrupt mask */ /* set timer 0 */ prm0 = 0b11110010; /* both rising and falling edges */ /* count clock is fx/2^6 */ crc0 = 0b00000101; /* set cr00 and cr01 to capture register */ tmc0 = 0b00000100; /* start in free-run mode */ ei(); while(1){ /* dummy loop */ if(data[0] != 0) /* ti00 measurement completion check */ { tmmk01 = 1; /* inttm01 interrupt prohibited for exclusive operation */ length = data[1]; /* read measurement results */ data[0] = 0; /* clear end flag */ tmmk01 = 0; /* exclusive operation completed */ } if(data[3] != 0) /* ti01 measurement completion check */ { tmmk00 = 1; /* inttm00 interrupt prohibited for exclusive operation */ length2 = data[4]; /* read measurement results */ data[3] = 0; /* clear end flag */ tmmk00 = 0; /* exclusive operation completed */ } } } 153 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud /* inttm00 interrupt function */ void intervalint() { unsigned int work; /******************************************************/ /* */ /* define variables required for interrupt here */ /* */ /******************************************************/ work = cr00; /* read capture value */ data[4] = work - data[5]; /* calculate and update interval */ data[5] = work; /* update read value */ data[3] = 0xffff; /* set measurement completion flag*/ /********************************************************/ /* */ /* define variables required for interrupt below */ /* */ /********************************************************/ } /* inttm01 interrupt function */ void intervalint2() { unsigned int work; /******************************************************/ /* */ /* define variables required for interrupt here */ /* */ /******************************************************/ work = cr01; /* read capture value */ data[1] = work - data[2]; /* calculate and update interval */ data[2] = work; /* update read value */ data[0] = 0xffff; /* set measurement completion flag*/ /********************************************************/ /* */ /* define variables required for interrupt below */ /* */ /********************************************************/ } 154 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud 6.5.4 pulse width measurement by restart /**************************************************************************/ /* */ /* timer 0 operation sample */ /* pulse width measurement example by restart */ /* measurement results up to 16 bits, not to be checked for errors */ /* data[0]: end flag */ /* data[1]: measurement results (pulse width) */ /* data[2]: previous read value */ /* */ /**************************************************************************/ #pragma sfr #pragma ei #pragma di #pragma interrupt inttm01 intervalint rb2 unsigned int data[3]; /* data area */ void main(void) { unsigned int length; pcc = 0x0; /* set high-speed operation mode */ data[0] = 0; data[1] = 0; data[2] = 0; /* set port */ pm3.2 = 1; /* set p32 as input */ /* set interrupt */ tmmk01 = 0; /* cancel inttm01 interrupt mask */ /* set timer 0 */ prm0 = 0b00110010; /* both rising and falling edges */ /* count clock is fx/2^6 */ crc0 = 0b00000100; /* set cr01 to capture register */ tmc0 = 0b00001000; /* clear & start at ti00 valid edge */ ei(); while(1){ /* dummy loop */ if(data[0] != 0) /* wait for ti00 measurement completion */ { tmmk01 = 1; /* prohibit inttm01 for exclusive operation */ length = data[1]+data[2]; /* cycle calculation based on measurement results */ data[0] = 0; /* clear end flag */ tmmk01 = 0; /* exclusive operation completed */ } } } /* timer 0 interrupt function */ void intervalint() { /******************************************************/ /* */ /* define variables required for interrupt here */ /* */ /******************************************************/ data[2] = data[1]; /* update old data */ data[1] = cr01; /* update read value */ data[0] = 0xffff; /* set measurement completion flag*/ /********************************************************/ /* */ /* define variables required for interrupt below */ /* */ /********************************************************/ } 155 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud 6.5.5 ppg output /******************************************************************************/ /* */ /* timer 0 ppg mode setting example */ /* cycle set to 98 as intervaltm0 */ /* active period set to 49 as active_time */ /* array ppgdata prepared as data area for rewriting */ /* [0]: active period (0000: no change, 0xffff: stop) */ /* [1]: cycle (0000: no change) */ /* ppgdata to be checked at every inttm00, and changed if required. */ /* therefore, if change is required, set the change data in ppgdata. */ /* when changed, ppgdata cleared to 0000. */ /* */ /******************************************************************************/ #pragma sfr #pragma ei #pragma di #define intervaltm0 98 /* cycle data to be set to cr00 */ #define active_time 49 /* initial value data of cr01 */ #pragma interrupt inttm00 ppgint rb2 unsigned int ppgdata[2]; /* data area to be set to timer 0 */ void main(void) { pcc = 0x0; /* set high-speed operation mode */ ppgdata[0] = 0; ppgdata[1] = 0; /* set port */ p3 = 0b11111101; /* clear p31 */ pm3.1 = 0; /* set p31 to output */ /* set interrupt */ tmmk00 = 0; /* cancel inttm00 interrupt mask */ /* set timer 0 */ prm0 = 0b00000010; /* count clock is fx/2^6 */ crc0 = 0b00000000; /* set cr00 and cr01 to compare register */ cr00 = intervaltm0; /* set initial value of cycle */ cr01 = active_time; /* set initial value of active period */ toc0 = 0b00010111; /* inverted on match between cr00 and cr01, initial value l */ tmc0 = 0b00001100; /* clear & start on match between tm0 and cr00 */ ei(); while(1); } /* timer 0 interrupt function */ void ppgint() { unsigned int work; work = ppgdata[0]; if (work != 0) { cr01 = work; ppgdata[0] = 0; if (work == 0xffff) { tmc0 = 0b00000000; /* stop timer */ } } work = ppgdata[1]; if (work != 0) { cr00 = work; ppgdata[1]=0; } } 156 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud 6.6 notes on 16-bit timer/event counter 0 (1) error on starting timer an error of up to 1 clock occurs from when the timer is started until a match signal is generated. this is because 16-bit timer counter 0 (tm0) is started asynchronously to the count pulse. figure 6-32. start timing of 16-bit timer counter (2) setting of 16-bit capture/compare register (in start & clear mode on match between tm0 and cr00) set 16-bit capture/compare registers 00 and 01 (cr00 and cr01) to a value other than 0000h (one pulse cannot be counted). (3) operation after changing value of compare register during timer count operation if a new value written to 16-bit capture/compare register 00 (cr00) is less than the value of 16-bit timer counter 0 (tm0), tm0 continues counting, overflows, and starts counting again from 0. therefore, if the new value of cr00 (m) is less than the old value (n), it is necessary to restart the timer after changing the value of cr00. figure 6-33. timing after changing value of compare register during timer count operation remark n > x > m tm0 count value 0000h 0001h 0002h 0004h count pulse timer starts 0003h cr00 nm count pulse tm0 count value x 1 x ffffh 0000h 0001h 0002h 157 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud (4) data retention timing of capture register when a capture trigger is input while a 16-bit capture/compare register (cr00/cr01) is being read, cr00/ cr01 continues the normal capture operation, but the read value at this time is not guaranteed. however, the interrupt request flag (tmif00/tmif01) is set as a result of detecting the valid edge. figure 6-34. data retention timing of capture register (5) setting of valid edge set the valid edge of the ti00/p32 pin after clearing bits 2 and 3 (tmc02 and tmc03) of 16-bit timer mode control register 0 to 0, 0, and stopping the timer operation. the valid edge is specified by using bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). (6) re-triggering one-shot pulse (a) one-shot pulse output with software trigger do not set ospt to 1 while the one-shot pulse is being output. to output the one-shot pulse again, wait until the inttm00 interrupt, which occurs on a match between tm0 and cr00, has occurred. (b) one-shot pulse output with external trigger the external trigger is ignored even if it is generated again while the one-shot pulse is being output. (c) one-shot pulse output function when using the software trigger for one-shot pulse output, fix the level of the ti00/p32 and ti01/p33 pins to either the high or low level. otherwise, the external trigger will remain valid even when the software trigger is used, and the timer will be cleared and started when the level of the ti00/p32 or ti01/p33 pin changes, resulting in unexpected output of the pulse. n x capture operation n + 1 n + 1 n + 2 m m + 1 m + 1 m + 2 tm0 count value edge input interrupt request flag capture read signal cr01 interrupt value count pulse the read value is not guaranteed. 158 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud (7) operation of ovf0 flag (a) ovf0 flag setting the ofv0 flag is set to 1 in the following case. when one of clear & start mode on match between tm0 and cr00, clear & start mode on ti00 valid edge, or free-running mode is selected. cr00 is set to ffffh. tm0 is counted up from ffffh to 0000h. figure 6-35. operation timing of ovf0 flag (b) ovf0 flag clear even if the ovf0 flag is cleared before the next count clock is counted (before tm0 becomes 0001h) after tm0 has overflowed, the ovf0 flag is set again and the clear becomes invalid. count pulse cr00 tm0 ovf0 inttm00 ffffh fffeh ffffh 0000h 0001h 159 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud (8) conflicting operations (a) if the read period and capture trigger input conflict if the read period and inputting a capture trigger conflict while 16-bit capture/compare registers 00 and 01 (cr00 and cr01) are used as capture registers, the capture operation takes precedence and the read data is undefined. however, the interrupt request flags (tmif00/tmif01) are set when the valid edge is detected. (b) if the match timing of the write period and tm0 conflict when 16-bit capture/compare registers 00 and 01 (cr00, cr01) are used as capture registers, because match detection cannot be performed correctly if the match timing of the write period and 16-bit timer counter 0 (tm0) conflict, do not write to cr00 and cr01 close to the match timing. (9) timer operation <1> even if 16-bit timer counter 0 (tm0) is read, its value is not captured to 16-bit capture/compare register 01 (cr01). <2> while the timer is stopped, signals input to the ti00 and ti01 pins are not accepted regardless of the operating mode of the cpu. <3> the one-shot pulse output operates correctly only in the free-running mode or the mode in which tm0 is cleared and started at the valid edge of ti00. in the mode in which tm0 is cleared and started on a match between tm0 and cr00, the one-shot operation cannot be performed because tm0 does not overflow. (10) capture operation <1> if the ti00 valid edge is specified as the count clock, a capture operation by the capture register specified as the trigger for ti00 is not possible. <2> if both the rising and falling edges are selected as the valid edges of ti00, cr00 does not perform a capture operation. <3> to ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 0 (prm0). figure 6-36. cr01 capture operation with rising edge specified <4> the capture operation is performed at the fall of the count clock. interrupt request input (inttm00, inttm01), however, occurs at the rise of the next count clock. count clock tm0 ti00 rising edge detection cr01 inttm01 n 3n 2n 1 n n+1 n 160 chapter 6 16-bit timer/event counter 0 user s manual u12790ej2v0ud (11) compare operation <1> when a 16-bit timer capture/compare register (cr00/cr01) is overwritten during timer operation, a match interrupt may be generated or the clear operation may not be performed normally if that value is close to or larger than the timer value. <2> the capture operation may not be performed for cr00/cr01 set to compare mode even if a capture trigger is input. (12) edge detection <1> if the ti00 pin or the ti01 pin is high level immediately after system reset and the rising edge or both the rising and falling edges are specified as the valid edge of the ti00 pin or ti01 pin to enable 16-bit timer counter 0 (tm0) operation, a rising edge is detected immediately. be careful when pulling up the ti00 pin or the ti01 pin. however, the rising edge is not detected at restart after the operation has been stopped. <2> the sampling clock used to eliminate noise differs when the ti00 valid edge is used as the count clock and when it is used as a capture trigger. in the former case, the count clock is f x /2 3 , and in the latter case the count clock is selected by prescaler mode register 0 (prm0). the capture operation is not performed until the valid edge is sampled and the valid level is detected twice, thus eliminating noise with a short pulse width. (13) stop mode setting stop the timer operation before setting stop mode; otherwise the timer may malfunction when the main system clock starts. 161 user? manual u12790ej2v0ud chapter 7 8-bit timer/event counters 50, 51 7.1 functions of 8-bit timer/event counters 50, 51 8-bit timer/event counters 50 and 51 have the following two modes. mode in which an 8-bit timer/event counter is used alone (single mode) mode in which the two timer/event counters are connected in cascade (cascade connection mode with a resolution of 16 bits) these two modes are explained below. (1) mode in which an 8-bit timer/event counter is used alone (single mode) the timer/event counter operates as an 8-bit timer/event counter. in this mode, the following functions can be used. <1> interval timer interrupt requests are generated at the preset interval. number of counts: 1 to 256 <2> external event counter the number of pulses with high/low level widths in a signal input externally can be measured. <3> square-wave output a square wave with an arbitrary frequency can be output. cycle: (1 2 to 256 2) count clock cycle <4> pwm output a pulse with an arbitrary duty ratio can be output. cycle: count clock 256 duty ratio: set value of compare register/256 (2) mode in which the two timer/event counters are connected in cascade (cascade connection mode with a resolution of 16 bits) by combining the two 8-bit timer/event counters, they can operate as a 16-bit timer/event counter. in this mode, the following functions can be used. interval timer with 16-bit resolution external event counter with 16-bit resolution square-wave output with 16-bit resolution figures 7-1 and 7-2 show the block diagrams of 8-bit timer/event counters 50 and 51. 162 chapter 7 8-bit timer/event counters 50, 51 user? manual u12790ej2v0ud figure 7-1. block diagram of 8-bit timer/event counter 50 figure 7-2. block diagram of 8-bit timer/event counter 51 notes 1. timer output f/f 2. pwm output f/f internal bus 8-bit compare register 50 (cr50) 8-bit timer counter 50 (tm50) ti50/p34 f x /2 5 f x /2 7 f x /2 9 f x /2 11 f x /2 3 match ovf clear 3 selector tcl502 tcl501 tcl500 timer clock select register 50 (tcl50) internal bus tce50 tmc506 tmc504 lvs50 lvr50 tmc501 toe50 level inversion timer mode control register 50 (tmc50) s r s q r inv selector note 1 note 2 inttm50 to50/p130 f x /2 output latch (p130) selector selector mask circuit internal bus 8-bit compare register 51 (cr51) 8-bit timer counter 51 (tm51) ti51/p35 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 match ovf clear 3 tcl512 tcl511 tcl510 internal bus tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 level inversion s r q r inv selector selector selector selector inttm51 to51/p131 s f x /2 11 output latch (p131) mask circuit timer clock select register 51 (tcl51) timer mode control register 51 (tmc51) note 1 note 2 163 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud 7.2 configuration of 8-bit timer/event counters 50, 51 8-bit timer/event counters 50 and 51 consist of the following hardware. table 7-1. configuration of 8-bit timer/event counters 50 and 51 item configuration timer counter 8-bit timer counters 50 and 51 (tm50 and tm51) register 8-bit compare registers 50 and 51 (cr50 and cr51) timer input ti50, ti51 timer output to50 and to51 control registers timer clock select registers 50 and 51 (tcl50 and tcl51) 8-bit timer mode control registers 50 and 51 (tmc50 and tmc51) port mode register 3 (pm3) port 13 (p13) (1) 8-bit timer counters 50 and 51 (tm50 and tm51) tm50 and tm51 are 8-bit read-only registers that count the count pulses. the counter is incremented at the rising edge of the count clock. when tm50 and tm51 are cascaded and used as a 16-bit timer, their values can be read by using a 16-bit memory manipulation instruction. however, because tm50 and tm51 are connected by the internal 8-bit bus, tm50 and tm51 are read separately in this order. therefore, read the value of tm50 and tm51 when used as a 16-bit timer twice for comparison, taking changes in the value during counting into consideration. if the count value is read while the timer is operating, stop input of the count clock note , and read the count value at that point. the count value is cleared to 00h in the following cases. <1> when reset is input <2> when tce5n is cleared <3> upon a match between tm5n and cr5n in the mode in which the timer is cleared and started on a match between tm5n and cr5n note an error may occur in the count. select a count clock that has a high/low level longer than two cycles of the cpu clock. caution in cascade connection mode, the count value is reset to 0000h when tce50 of the lowest timer is cleared. remark n = 0, 1 164 chapter 7 8-bit timer/event counters 50, 51 user? manual u12790ej2v0ud (2) 8-bit compare registers 50 and 51 (cr50 and cr51) when cr5n is used as a compare register in other than pwm mode, the value set to cr5n is constantly compared with 8-bit timer counter 5n (tm5n) count value, and an interrupt request (inttm5n) is generated if they match. in pwm mode, the to5n pin goes to the active level by the overflow of tm5n. when the values of tm5n and cr5n match, the to5n pin goes to the inactive level. it is possible to rewrite the value of cr5n within 00h to ffh during a count operation. when tm50 and tm51 can be connected in cascade and used as a 16-bit timer, cr50 and cr51 operate as a 16-bit compare register. this register compares the count value with the register value, and if the values match, an interrupt request (inttm50) is generated. the inttm51 interrupt request is also generated at this time, so mask the inttm51 interrupt request. set cr5n using an 8-bit memory manipulation instruction. reset input makes cr5n undefined. caution in the cascade connection mode, stop the timer operation before setting data. remark n = 0, 1 165 chapter 7 8-bit timer/event counters 50, 51 user? manual u12790ej2v0ud 7.3 registers controlling 8-bit timer/event counters 50, 51 the following four types of registers control 8-bit timer/event counters 50 and 51. timer clock select registers 50 and 51 (tcl50 and tcl51) 8-bit timer mode control registers 50 and 51 (tmc50 and tmc51) port mode register 3 (pm3) port 13 (p13) (1) timer clock select registers 50 and 51 (tcl50 and tcl51) these registers select the count clock of 8-bit timer/event counters 50 and 51 (tm50 and tm51) and the valid edge of the ti50 and ti51 inputs. tcl50 and tcl51 are set by using an 8-bit memory manipulation instruction. the values of these registers are cleared to 00h after reset. figure 7-3. format of timer clock select register 50 (tcl50) tcl502 tcl501 tcl500 selection of count clock 0 0 0 falling edge of ti50 0 0 1 rising edge of ti50 010f x /2 (3.15 mhz) 011f x /2 3 (788 khz) 100f x /2 5 (197 khz) 101f x /2 7 (49.2 khz) 110f x /2 9 (12.3 khz) 111f x /2 11 (3.08 khz) cautions 1. when changing the data of tcl50, be sure to stop the timer operation. 2. be sure to reset bits 3 to 7 to ?? remarks 1. in the cascade connection mode, the only setting of the count clock in tcl50 is valid. 2. f x : system clock oscillation frequency 3. ( ): f x = 6.3 mhz 76543 000 tcl502 tcl501 tcl500 00 210 symbol tcl50 address ff84h after reset 00h r/w r/w 166 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud figure 7-4. format of timer clock select register 51 (tcl51) tcl512 tcl511 tcl510 selecttion of count clock 0 0 0 falling edge of ti51 0 0 1 rising edge of ti51 010f x /2 (3.15 mhz) 011f x /2 3 (788 khz) 100f x /2 5 (197 khz) 101f x /2 7 (49.2 khz) 110f x /2 9 (12.3 khz) 111f x /2 11 (3.08 khz) cautions 1. when changing the data of tcl51, be sure to stop the timer operation. 2. be sure to reset bits 3 to 7 to ?? remarks 1. in the cascade connection mode, the setting of tcl51 is invalid. 2. f x : system clock oscillation frequency 3. ( ): f x = 6.3 mhz (2) 8-bit timer mode control registers 50 and 51 (tmc50 and tmc51) tmc50 and tmc51 are registers that are used for the following. <1> controlling count operation of 8-bit timer counters 50 and 51 (tm50 and tm51) <2> selecting operation mode of 8-bit timer counters 50 and 51 (tm50 and tm51) <3> selecting single mode or cascade connection mode (tmc51 only) <4> setting status of timer output f/f (flip-flop) <5> controlling timer f/f or selecting active level in pwm (free-running) mode <6> controlling timer output tmc50 and tmc51 can be set by using a 1-bit or 8-bit memory manipulation instruction. they are cleared to 00h after reset. figures 7-5 and 7-6 show the formats of tmc50 and tmc51. 76543 000 tcl512 tcl511 tcl510 00 210 symbol tcl51 address ff87h after reset 00h r/w r/w 167 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud figure 7-5. format of 8-bit timer mode control register 50 (tmc50) tce50 control of count operation of tm50 0 counter cleared to 0 and count operation disabled (prescaler disabled) 1 count operation starts tmc506 selection of operating mode of tm50 0 mode of clearing and starting tm50 on match between tm50 and cr50 1 pwm (free-running) mode tmc504 be sure to reset this bit to 0 . lvs50 lvr50 setting of status of timer output f/f 0 0 not affected 0 1 timer output f/f reset to 0 1 0 timer output f/f set to 1 1 1 setting prohibited tmc501 other than pwm mode (tmc506 = 0) pwm mode (tmc506 = 1) control of timer f/f selection of active level 0 inversion operation disabled active high 1 inversion operation enabled active low toe50 control of timer output 0 output (port mode) disabled 1 output enabled caution be sure to reset bit 4 (tmc504) to ?? remarks 1. the pwm output becomes inactive when tce50 = 0 in the pwm mode. 2. lvs50 and lvr50 are 0 when read after data has been set. <7> tce50 6 tmc506 5 0 4 tmc504 <3> lvs50 <2> lvr50 1 tmc501 <0> toe50 symbol tmc50 address ff85h after reset 00h r/w r/w 168 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud figure 7-6. format of 8-bit timer mode control register 51 (tmc51) tce51 control of count operation of tm51 0 counter cleared to 0 and count operation disabled (prescaler disabled) 1 count operation starts tmc516 selection of operating mode of tm51 0 mode of clearing and starting tm51 on match between tm51 and cr51 1 pwm (free-running) mode tmc514 selection of single mode or cascade connection mode 0 single mode 1 cascade connection mode (connected to lower timer (tm50)) lvs51 lvr51 setting of status of timer output f/f 0 0 not affected 0 1 timer output f/f reset to 0 1 0 timer output f/f set to 1 1 1 setting prohibited tmc511 other than pwm mode (tmc516 = 0) pwm mode (tmc516 = 1) control of timer f/f selection of active level 0 inversion operation disabled active high 1 inversion operation enabled active low toe51 control of timer output 0 output (port mode) disabled 1 output enabled remarks 1. the pwm output becomes inactive when tce51 = 0 in the pwm mode. 2. lvs51 and lvr51 are 0 when read after data has been set. <7> 6 5 4 <3> tce51 tmc516 0 lvr51 tmc511 toe51 tmc514 lvs51 <2> 1 <0> symbol tmc51 address ff88h after reset 00h r/w r/w 169 chapter 7 8-bit timer/event counters 50, 51 user? manual u12790ej2v0ud (3) port mode register 3 (pm3) this register sets port 3 i/o in 1-bit units. when using the p34/ti50 pin for timer input, set pm34 to 1. when using the p35/ti51 pin for timer input, set pm35 to 1. when using the p130/to50 pin for timer output, set the output latch of p130 to 0. when using the p131/to51 pin for timer output, set the output latch of p131 to 0. pm3 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 7-7. format of port mode register 3 (pm3) pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 76543210 symbol pm3 ff23h ffh r/w address after reset r/w pm3n selection of p3n pin i/o mode (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 170 chapter 7 8-bit timer/event counters 50, 51 user? manual u12790ej2v0ud 7.4 operations of 8-bit timer/event counters 50, 51 7.4.1 operation as interval timer (8-bit) the 8-bit timer/event counter operates as an interval timer that repeatedly generates an interrupt request at the interval specified by the count value preset to 8-bit compare register 5n (crn). when the count value of 8-bit timer counter 5n (tm5n) matches the value set to cr5n, the value of tm5n is cleared to 0. tm5n continues counting and an interrupt request signal (inttm5n) is generated. the count clock of tm5n can be selected by using bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock select register 5n (tcl5n). [setting] <1> set each register. tcl5n: select a count clock. cr5n: set a compare value. tmc5n: select count operation stop and clear & start mode on match between tm5n and cr5n (tmc5n = 0000 0b: = don? care). <2> the count operation is started when tec5n is set to 1. <3> inttm5n is generated when the values of tm5n and cr5n match (tm5n is cleared to 00h). <4> after that, inttm5n is repeatedly generated at fixed intervals. to stop the count operation, clear tce5n to 0. remark n = 0 or 1 171 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud figure 7-8. timing of interval timer operation (1/3) (a) basic operation remarks 1. interval time = (n + 1) t n = 00h to ffh 2. n = 0 or 1 t 00 01 nn nn n 00 01 n 00 01 n cr5n count clock interval time count starts interval time clear clear interrupt request acknowledged interrupt request acknowledged interval time tm5n count value tce5n inttm5n to5n 172 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud figure 7-8. timing of interval timer operation (2/3) (b) when cr5n = 00h (c) when cr5n = ffh t count clock tm5 cr5n tce5n inttm5n to5n interval time 00h 00h 00h 00h 00h t tm5n count clock cr5n tce5n inttm5n to5n 01 fe ff 00 fe ff 00 ff ff ff interval time interrupt acknowl- edged interrupt acknowledged remark n = 0 or 1 173 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud figure 7-8. timing of interval timer operation (3/3) (d) operation when cr5n is changed (m < n) (e) operation when cr5n is changed (m > n) count clock tm5 cr5n tce5n inttm5n to5n n 00h m n ffh 00h m 00h nm cr5n is changed. tm5n overflows because m < n h count clock tm5 cr5n tce5n inttm5n to5n n 1n n 00h 01h n m 1 m 00h 01h m cr5n is changed. h remark n = 0 or 1 174 chapter 7 8-bit timer/event counters 50, 51 user? manual u12790ej2v0ud 7.4.2 operation as external event counter the external event counter counts the number of clock pulses input from an external source to the ti5n pin using 8-bit timer counter 5n (tm5n). each time the valid edge specified by timer clock select register 5n (tcl5n) is input to ti5n, the value of tm5n is incremented. either the rising or falling edge can be selected as the valid edge. when the count value of tm5n matches the value of 8-bit compare register 5n (cr5n), tm5n is cleared to 0, and an interrupt request signal (inttm5n) is generated. after that, each time the value of tm5n matches the value of cr5n, inttm5n is generated. [setting] <1> set each register. tcl5n: select rising or falling edge of ti5n input. rising edge of ti5n tcl5n = 00h falling edge of ti5n tcl5n = 01h cr5n: set a compare value. tmc5n: select count operation stop, clear & start mode on match between tm5n and cr5n, timer f/f inverted operation disable, timer output disable. (tmc5n = 0000 00b, = don? care) <2> when tce5n = 1 is set, the number of pulses input from ti5n is counted. <3> inttm5n is generated when the values of tm5n and cr5n match (tm5n is cleared to 00h). <4> after that, inttm5n is generated each time when the values of tm5n and cr5n match. remark n = 0 or 1 figure 7-9. operation timing of external event counter (with rising edge specified) ti5n tm5n count value cr5n inttm5n 00 01 02 03 04 05 n ? 1 n 00 01 02 03 n remarks 1. n = 00h to ffh 2. n = 0 or 1 175 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud 7.4.3 square-wave output operation (8-bit resolution) the 8-bit timer/event counter (tm5n) can be used to output a square wave with any frequency at time intervals specified by the value preset to 8-bit compare register 5n (cr5n). when bit 0 (toe5n) of 8-bit timer mode control register 5n (tmc5n) is set to 1, the output status of to5n is inverted at the interval specified by the count value preset to cr5n. in this way, a square wave (duty factor = 50%) of any frequency can be output. [setting] <1> set each register. reset the port latches (p130 and p131) to 0 . tcl5n: select a count clock. cr5n: set a compare value. tmc5n: select clear & start mode on match between tm5n and cr5n. lvs5n lvr5n setting of status of timer output f/f 1 0 high-level output 0 1 low-level output enable inverting the timer f/f. enable the timer output toe5n = 1. <2> when tce5n is set to 1, the count operation is started. <3> when the value of tm5n matches as the value of cr5n, the timer output f/f is inverted. in addition, inttm5n is generated, and tm5n is cleared to 00h. <4> after that, the timer output f/f is inverted at fixed intervals, and a square wave is output from to5n. remark n = 0 or 1 figure 7-10. timing of square-wave output operation note the initial value of to5n output can be set by using bits 2 and 3 (lvr5n and lvs5n) of 8-bit timer mode control register 5n (tmc5n). remark n = 0 or 1 tm5n count value count starts count clock 00h 01h 02h n ? 1n n 00h n ? 1 n 00h 01h 02h cr5n inttm5n to5n note 176 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud 7.4.4 8-bit pwm output operation the 8-bit timer/event counter can be used for pwm output when bit 6 (tmc5n6) of 8-bit timer mode control register 5n (tmc5n) is set to 1. a pulse with the duty factor determined by the value set to 8-bit compare register 5n (cr5n) is output from to5n. set the active level width of the pwm pulse to cr5n. the active level is selected by bit 1 (tmc5n) of tmc5n. the count clock can be selected by bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock select register n (tcl5n). pwm output can be enabled or disabled by bit 0 (toe5n) of tmc5n. caution the value of cr5n can be rewritten only once in once cycle in the pwm mode. remark n = 0 or 1 (1) basic operation of pwm output [setting] <1> set each register. reset the port latches (p130 and p131) note to 0 . tcl5n: select a count clock. cr5n: set a compare value. tmc5n: select count operation stop, pwm mode, timer output f/f not affected. tmc5n1 active level selection 0 active high 1 active low enable timer output. (tmc5n = 01000001b or 01000011b) <2> the count operation is started when tce5n = 1 is set. to stop the count operation, set tce5n to 0. note 8-bit timer/event counter 50: p130 8-bit timer/event counter 51: p131 [operation of pwm output] <1> when the count operation is started, the pwm output (output from to5n) remains inactive until an overflow occurs. <2> when an overflow occurs, the active level is output. this active level is output until the value of cr5n matches the count value of 8-bit timer counter 5n (tm5n). <3> the pwm output remains inactive after cr5n and the count value of tm5n have matched, until an overflow occurs again. <4> after that, <2> and <3> are repeated until the count operation is stopped. <5> when the count operation is stopped because tce5n is cleared to 0, the pwm output becomes inactive. remark n = 0 or 1 177 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud figure 7-11. operation timing of pwm output (a) basic operation (when active level = h) (b) when cr5n = 0 (c) when cr5n = ffh count clock tm5n cr5n tce5n inttm5n to5n 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h n active level inactive level active level count clock tm5n cr5n tce5n inttm5n to5n inactive level inactive level 01h 00h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h 00h n + 2 l tm5n count clock cr5n tce5n inttm5n to5n 01h 00h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h ffh n + 2 inactive level active level inactive level active level inactive level remark n = 0 or 1 178 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud (2) operation when cr5n is changed figure 7-12. timing of operation when cr5n is changed (a) if value of cr5n is changed from n to m when tm5n > cr5n (b) if value of cr5n is changed from n to m when tm5n < cr5n caution the value of cr5n can be changed only once in one cycle in the pwm mode. remark n = 0 or 1 count clock tm5n cr5n tce5n inttm5n to5n cr5n changed (n m) n n + 1n + 2 ffh 00h 01h m m + 1m + 2 ffh 00h 01h 02h m m + 1m + 2 n 02h m h count clock tm5n cr5n tce5n inttm5n to5n n n + 1n + 2 ffh 00h 01h n n + 1n + 2 ffh 00h 01h 02h n 02h n h 03h m m m + 1m + 2 cr5n changed (n m) 179 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud 7.4.5 operation as interval timer (16-bit) the 8-bit timer/event counters are used together in 16-bit timer/counter mode when bit 4 (tmc514) of 8-bit timer mode control register 51 (tm51) is set to 1. in this mode, the 8-bit timer/event counters are used as a 16-bit interval timer that repeatedly generates an interrupt request at intervals specified by the count value preset to the 8-bit compare registers (cr50 and cr51). at this time, cr50 serves as the lower 8 bits of the 16-bit compare register, and cr51 serves as the higher 8 bits. [setting] <1> set each register. tcl50: select a count clock for tm50. the count clock for tm51, which is cascaded, does not have to be set. cr50 and cr51: set compare values (each compare value can be set in a range of 00h to ffh). tmc50 and tmc51: select clear & start mode on match between tm50 and cr50 (or between tm51 and cr51). tm50 tmc50 = 0000 0b : don t care tm51 tmc51 = 0001 0b : don t care <2> the count operation is started by setting tce51 of tmc51 to 1 first, and then tce50 of tmc50 to 1. <3> if the value of cascaded timer tm50 matches the value of cr50, inttm50 of tm50 is generated (tm50 and tm51 are cleared to 00h). <4> after that, inttm50 is repeatedly generated at fixed intervals. cautions 1. be sure to set the compare registers (cr50 and cr51) after stopping the operation of both timers (tce50 = tce51 = 0). 2. even if the 8-bit timer/counters are cascaded, inttm51 of tm51 is generated when the count value of tm51 matches cr51. be sure to mask tm51 to disable this interrupt. 3. set tce50 and tce51 in the order of tm51 then tm50. 4. counting can be restarted or stopped just by setting or resetting tce50 of tm50 to 1 or 0. figure 7-13 shows a timing example in the 16-bit cascade connection mode. 180 chapter 7 8-bit timer/event counters 50, 51 user? manual u12790ej2v0ud figure 7-13. 16-bit cascade connection mode count clock tm50 tm51 cr50 cr51 tce50 tce51 inttm50 to50 operation enabled. count starts. interval time 00h 01h n n + 1 ffh 00h ffh 00h ffh 00h 01h n 00h 01h a 00h 00h 01h 02h m 1 m 00h b 00h n m interrupt request generated. level inverted. counter cleared. operation stops 181 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud 7.5 program list caution the following sample program is shown as an example to describe the operation of semiconductor products and their applications. therefore, when applying the following information to your devices, design the devices after performing evaluation on your own responsibility. 7.5.1 interval timer (8-bit) /*************************************************************************************/ /* */ /* timer 50 operation sample */ /* interval timer setting example (frequency change by interrupt processing) */ /* data[0]: data set flag (value changed when other than 00) */ /* data[1]: set data */ /* */ /*************************************************************************************/ #pragma sfr #pragma ei #pragma di #pragma interrupt inttm50 intervalint rb2 unsigned char data[2]; /* data area */ void main(void) { pcc = 0x0; /* set high-speed operation mode */ data[0] = 0; /* clear data area */ data[1] = 0; /* set port */ p13 = 0b11111110; /* clear p130 when using to50 */ /* set interrupt */ tmmk50 = 0; /* clear inttm50 interrupt mask */ /* set timer 50 */ tmc50 = 0b00000111; /* clear & start mode, initial value l */ cl50 = 0b00000101; /* both rising and falling edges */ /* count clock is fx/2^6 */ cr50 = 98; /* set interval to 1 ms as initial value */ tce50 = 1; /* timer start */ ei(); while(1); /* dummy loop */ } /* inttm50 interrupt function */ void intervalint() { if(data[0] != 0) { cr50 = data[1]; /* set new set value */ data[0] = 0; /* clear request flag */ } } 182 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud 7.5.2 external event counter /***************************************************************/ /* */ /* timer 50 operation sample */ /* event counter setting example */ /* data: count up flag */ /* */ /***************************************************************/ #pragma sfr #pragma ei #pragma di #pragma interrupt inttm50 intervalint rb2 unsigned char data; /* data area */ void main(void) { pcc = 0x0; /* set high-speed operation mode */ data = 0; /* clear data area */ /* set port */ pm3.4 = 1; /* set p34 to input */ /* set interrupt */ tmmk50 = 0; /* clear inttm50 interrupt mask */ /* set timer 50 */ tmc50 = 0b00000000; /* clear & start mode */ tcl50 = 0b00000001; /* specify rising edge of ti50 */ cr50 = 0x10; /* set n = 16 as initial value */ tce50 = 1; /* timer start */ ei(); /*************************************************************/ /* */ /* describe the processing to be executed */ /* */ /*************************************************************/ while(data == 0); /* wait for count up */ /*************************************************************/ /* */ /* describe the processing after count up below */ /* */ /*************************************************************/ } /* inttm50 interrupt function */ void intervalint() { data = 0xff; /* set count up flag */ tce50 = 0; /* timer stop */ } 183 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud 7.5.3 interval timer (16-bit) /***************************************************************/ /* */ /* timer 5 operation sample */ /* cascade connection setting example */ /* */ /***************************************************************/ #pragma sfr #pragma ei #pragma di #define intervaltm5 98 /* cycle data to be set to cr */ #pragma interrupt inttm50 ppgint rb2 unsigned char ppgdata[2]; /* data area to be set to timer 5 */ void main(void) { int interval; interval = intervaltm5; pcc = 0x0; /* select high-speed operation mode */ ppgdata[0] = 0; /* clear cr50 data */ ppgdata[1] = 0; /* clear cr51 data */ /* set port */ p13 = 0b11111110; /* clear p130 when using to50 */ /* set interrupt */ tmmk50 = 0; /* clear inttm50 interrupt mask */ tmmk51 = 1; /* set inttm51 interrupt mask */ /* set timer 5 */ tcl50 = 0b00000101; /* count clock is fx/2^6 */ cr50 = interval & 0xff; /* set lower compare register to cr50 */ cr51 = interval >> 8; /* set higher compare register to cr51 */ tmc50 = 0b00000111; /* inverted on match, initial value l */ tmc51 = 0b00010000; /* cascade mode */ tce51 = 1; tce50 = 1; /* timer starts */ ei(); while(1); } /* timer 5 interrupt function */ void ppgint() { unsigned int work; work = ppgdata[0]+ppgdata[1]*0x100; if (work != 0) { tce50 =0; cr51 = work >> 8; cr50 = work & 0xff; ppgdata[0] = 0; ppgdata[1] = 0; if (work != 0xffff) { tce50 = 1; /* timer resumes */ } } } 184 chapter 7 8-bit timer/event counters 50, 51 user s manual u12790ej2v0ud 7.6 notes on 8-bit timer/event counters 50, 51 (1) error on starting timer an error of up to 1 clock occurs after the timer has been started until a match signal is generated. this is because 8-bit timer counter 5n (tm5n) is started asynchronously to the count pulse. figure 7-14. start timing of 8-bit timer counter 5n count pulse tm5n count value 00h 01h 02h 03h 04h timer starts (2) stop mode setting be sure to clear tce5n to 0 to set the stop status, except when ti5n input is selected. otherwise, the timer may malfunction when the system clock starts oscillating. (3) reading tm5n (n = 0 or 1) during timer operation when tm5n is read during operation, the count clock is temporarily stopped. therefore, select a count clock with a high/low level longer than two cycles of the cpu clock. for example, when the cpu clock (f cpu ) is f x , the count clock to be selected should be f x /4 or less in order that tm5n can be read. remark n = 0 or 1 185 user? manual u12790ej2v0ud chapter 8 basic timer the basic timer is used for time management during program execution. 8.1 function of basic timer the basic timer generates an interrupt request signal (intbtm0) at time intervals of 100 ms. 8.2 configuration of basic timer figure 8-1. block diagram of basic timer caution with the pd178078 and 178098a subseries, a 4.5 mhz crystal resonator can be used in addition to the 6.3 mhz crystal resonator. if the system clock is used at a frequency of 4.5 mhz, set bit 0 (dtsck0) of the dts system clock select register (dtsck) to 1 (refer to note in 5.1). even if the system clock (6.3 or 4.5 mhz) is changed, the timing shown in figure 8-2 timing of basic timer operation is not changed. the first interrupt request signal (intbtm0) after the dtsck0 flag has been set is generated within 100 to 140 ms. the second signal and those that follow are generated at intervals of 100 ms. divider 6.3 mhz or 4.5 mhz intbtm0 186 chapter 8 basic timer user s manual u12790ej2v0ud 8.3 operation of basic timer an example of the operation of the basic timer is shown below. in this example, the basic timer operates as an interval timer that repeatedly generates an interrupt at time intervals of 100 ms. an interrupt request signal (intbtm0) is generated every 100 ms. the timer clock frequency is 10 hz. figure 8-2. timing of basic timer operation by polling the interrupt request flag (btmif0) of this basic timer by software, time management can be carried out. note that btmif0 is not a read & reset flag. figure 8-3. operation timing to poll btmif0 flag for the registers controlling the basic timer, refer to chapter 18 interrupt functions . timer clock (10 hz) btmif0 flag 1 when polled by software 0 is written by software always 1 unless 0 is written by software interrupt acknowledged timer clock (10 hz) intbtm0 interval time (100 ms) interval time interval time interrupt acknowledged 187 user? manual u12790ej2v0ud chapter 9 watchdog timer 9.1 watchdog timer functions the watchdog timer has the following functions. watchdog timer interval timer caution select the watchdog timer mode or the interval timer mode using the watchdog timer mode register (wdtm). (the watchdog timer and interval timer cannot be used simultaneously.) figure 9-1 shows a block diagram of the watchdog timer. figure 9-1. block diagram of watchdog timer f x /2 8 run clock input controller divider divided clock selector output controller intwdt reset wdt mode signal 3 division mode selector wdcs2 wdcs1 wdcs0 internal bus run wdtm4 wdtm3 watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) 188 chapter 9 watchdog timer user s manual u12790ej2v0ud (1) watchdog timer mode an inadvertent program loop is detected. upon detection of the inadvertent program loop, a non-maskable interrupt request or reset can be generated. table 9-1. watchdog timer inadvertent program loop detection time inadvertent program loop detection time 2 12 1/f x (650 s) 2 13 1/f x (1.30 ms) 2 14 1/f x (2.60 ms) 2 15 1/f x (5.20 ms) 2 16 1/f x (10.4 ms) 2 17 1/f x (20.8 ms) 2 18 1/f x (41.6 ms) 2 20 1/f x (166 ms) remark f x : system clock oscillation frequency ( ): f x = 6.3 mhz. (2) interval timer mode interrupt requests are generated at the preset time intervals. table 9-2. interval time interval time 2 12 1/f x (650 s) 2 13 1/f x (1.30 ms) 2 14 1/f x (2.60 ms) 2 15 1/f x (5.20 ms) 2 16 1/f x (10.4 ms) 2 17 1/f x (20.8 ms) 2 18 1/f x (41.6 ms) 2 20 1/f x (166 ms) remark f x : system clock oscillation frequency ( ): f x = 6.3 mhz. 189 chapter 9 watchdog timer user s manual u12790ej2v0ud 9.2 watchdog timer configuration the watchdog timer consists of the following hardware. table 9-3. configuration of watchdog timer item configuration control registers watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) 9.3 watchdog timer control registers the following two registers are used to control the watchdog timer. watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) 190 chapter 9 watchdog timer user? manual u12790ej2v0ud (1) watchdog timer clock select register (wdcs) this register sets the watchdog timer and overflow time of the interval timer. wdcs is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets wdcs to 00h. figure 9-2. format of watchdog timer clock select register (wdcs) remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 6.3 mhz. 0 7 0 6 0 0 4 0 3210 ff42h address wdcs symbol wdcs2 wdcs1 wdcs0 5 00h after reset r/w r/w 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 wdcs2 wdcs1 wdcs0 2 12 /f x 2 13 /f x 2 14 /f x 2 15 /f x 2 16 /f x 2 17 /f x 2 18 /f x 2 20 /f x watchdog timer/interval timer overflow time (650 s) (1.30 ms) (2.60 ms) (5.20 ms) (10.4 ms) (20.8 ms) (41.6 ms) (166 ms) 191 chapter 9 watchdog timer user? manual u12790ej2v0ud (2) watchdog timer mode register (wdtm) this register sets the watchdog timer operating mode and enables/disables counting. wdtm is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets wdtm to 00h. figure 9-3. format of watchdog timer mode register (wdtm) notes 1. once set to 1, run cannot be cleared to 0 by software. therefore, use reset input to clear run to 0. 2. once set to 1, wdtm3 and wdtm4 cannot be cleared to 0 by software. 3. wdtm starts interval timer operation as soon as run is set to 1. caution when run is set to 1 so that the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by the watchdog timer clock select register (wdcs). remark : don? care run <7> 0 6 0 wdtm4 4 wdtm3 3210 fff9h address wdtm symbol 000 5 00h after reset r/w r/w run 0 1 count enable/disable wdtm3 selection of watchdog timer operating mode note 2 wdtm4 interval timer mode note 3 (maskable interrupt occurs upon generation of an overflow.) watchdog timer mode 1 (non-maskable interrupt occurs upon generation of an overflow.) watchdog timer mode 2 (reset operation is activated upon generation of an overflow.) 0 1 0 1 1 count stop counter is cleared and counting starts. 192 chapter 9 watchdog timer user s manual u12790ej2v0ud 9.4 watchdog timer operations 9.4.1 operation as watchdog timer when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1, the watchdog timer operates to detect an inadvertent program loop. the watchdog timer count clock (inadvertent program loop detection time interval) can be selected using bits 0 to 2 (wdcs0 to wdcs2) of watchdog timer clock select register 2 (wdcs). the watchdog timer starts counting when bit 7 (run) of wdtm is set to 1. after the watchdog timer starts counting, set run to 1 again within the set inadvertent program loop time interval to clear the watchdog timer and start counting again. if run is not set to 1 and the inadvertent program loop detection time elapses, a system reset or non-maskable interrupt request is generated according to the value of wdtm bit 3 (wdtm3). the watchdog timer continues operating in the halt mode but it stops in the stop mode. thus, set run to 1 before the stop mode is set, clear the watchdog timer, and then execute the stop instruction. caution the actual inadvertent program loop detection time may be shorter than the set time by up to 0.5%. table 9-4. watchdog timer inadvertent program loop detection time inadvertent program loop detection time 2 12 1/f x (650 s) 2 13 1/f x (1.30 ms) 2 14 1/f x (2.60 ms) 2 15 1/f x (5.20 ms) 2 16 1/f x (10.4 ms) 2 17 1/f x (20.8 ms) 2 18 1/f x (41.6 ms) 2 20 1/f x (166 ms) remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 6.3 mhz. 193 chapter 9 watchdog timer user s manual u12790ej2v0ud 9.4.2 operation as interval timer the watchdog timer operates as an interval timer that generates interrupt requests repeatedly at an interval of the preset count value when bit 3 (wdtm3) and bit 4 (wdtm4) of the watchdog timer mode register (wdtm) are set to 1 and 0, respectively. the count clock (interval time) can be selected by using bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs). by setting bit 7 (run) of wdtm to 1, the watchdog timer starts operating as an interval timer. when the watchdog timer operates as interval timer, the interrupt mask flag (wdtmk) and priority specification flag (wdtpr) are validated and the maskable request interrupt (intwdt) can be generated. among the maskable interrupt requests, intwdt has the highest default priority. the interval timer continues operating in the halt mode but it stops in stop mode. thus, set run to 1 before the stop mode is set, clear the interval timer, and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless reset is input. 2. the interval time just after being set by wdtm may be shorter than the set time by up to 0.5%. table 9-5. interval timer interval time interval time 2 12 1/f x (650 s) 2 13 1/f x (1.30 ms) 2 14 1/f x (2.60 ms) 2 15 1/f x (5.20 ms) 2 16 1/f x (10.4 ms) 2 17 1/f x (20.8 ms) 2 18 1/f x (41.6 ms) 2 20 1/f x (166 ms) remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 6.3 mhz. 194 user? manual u12790ej2v0ud chapter 10 buzzer output controllers 10.1 functions of buzzer output controllers the pd178078 and 178098a subseries have the following two types of buzzer output controllers. beep0 buz beep0 outputs a square wave of the buzzer frequency selected by beep frequency select register 0 (beepcl0) from the beep0/p36 pin. buz outputs a square wave of the buzzer frequency selected by the clock output select register (cks) from the buz/p37 pin. figures 10-1 and 10-2 show the block diagrams of beep0 and buz. figure 10-1. block diagram of beep0 figure 10-2. block diagram of buz remark f x : system clock oscillation frequency internal bus bzo bcs bcs clock output select register (cks) buz/p37 f x /2 10 f x /2 11 f x /2 12 f x /2 13 output latch (p37) pm37 selector internal bus beep cl02 beep cl01 beep cl00 beep frequency select register 0 (beepcl0) beep0/p36 1 khz 1.5 khz 3 khz 4 khz output latch (p36) pm36 selector 195 chapter 10 buzzer output controllers user s manual u12790ej2v0ud 10.2 configuration of buzzer output controllers the buzzer output controllers consist of the following hardware. table 10-1. configuration of buzzer output controllers (1) beep0 item configuration control register beep frequency select register 0 (beepcl0) (2) buz item configuration control register clock output select register (cks) 10.3 registers controlling buzzer output controllers 10.3.1 beep0 beep0 is controlled by the following register. beep frequency select register 0 (beepcl0) (1) beep frequency select register 0 (beepcl0) this register selects the frequency of buzzer output. beepcl0 is set by a 1-bit or 8-bit memory manipulation instruction. this register is cleared to 00h after reset. 196 chapter 10 buzzer output controllers user s manual u12790ej2v0ud figure 10-3. format of beep frequency select register 0 (beepcl0) beep beep beep selection of frequency of cl02 cl01 cl00 beep0 output 0 buzzer output (port function) disabled 1 0 0 1 khz 0 0 1 3 khz 1 1 0 4 khz 1 1 1 1.5 khz cautions 1. the selected clock may not be correctly output during the period of 1 cycle immediately after the output clock has been changed. 2. the frequency of beep0 output (1 khz, 1.5 khz, 3 khz, or 4 khz) does not change even if the system clock (6.3 mhz or 4.5 mhz) is changed. 10.3.2 buz buz is controlled by the following register. clock output select register (cks) figure 10-4. format of clock output select register (cks) bzoe buz output enable/disable 0 low-level output 1 buzzer output enabled bcs1 bcs0 selection of output clock of buz 00f x /2 10 (6.15 khz) 01f x /2 11 (3.08 khz) 10f x /2 12 (1.54 khz) 11f x /2 13 (769 hz) f x : system clock oscillation frequency ( ): f x = 6.3 mhz 76543 00000 2 beep cl02 1 beep cl01 0 beep cl00 symbol beep cl0 address ff41h after reset 00h r/w r/w <7>6543 bzoe bcs1 bcs0 0 0 2 0 1 0 0 0 symbol cks address ff40h after reset 00h r/w r/w 197 chapter 10 buzzer output controllers user s manual u12790ej2v0ud 10.4 operation of buzzer output controllers the buzzer frequency is output using the following procedure. (1) beep0 <1> select the buzzer output frequency by using bits 0 to 2 (beepcl00 to beepcl02) of beep frequency select register 0 (beepcl0). <2> reset the output latch of p36 to 0. <3> reset bit 6 (pm36) of port mode register 3 to 0 (set the output mode). (2) buz <1> select the buzzer output frequency by using bits 5 and 6 (bcs0 and bcs1) of the clock output select register (cks) (disable buzzer output). <2> set bit 7 (bzoe) of cks to 1 and enable buzzer output. <3> reset the output latch of p37 to 0. <4> reset bit 7 (pm37) of port mode register 3 to 0 (set output mode). 198 user? manual u12790ej2v0ud chapter 11 a/d converter 11.1 a/d converter functions the a/d converter converts an analog input into a digital value. it consists of 8 channels (ani0 to ani7) with 8-bit resolution. the conversion method is based on successive approximation and the conversion result is held in 8-bit a/d conversion result register 3 (adcr3). conversion is started by setting a/d converter mode register 3 (adm3). select one analog input channel from ani0 to ani7 and carry out a/d conversion. when a/d conversion is completed, the next a/d conversion is started immediately. each time an a/d conversion operation ends, an interrupt request (intad) is generated. 11.2 a/d converter configuration the a/d converter consists of the following hardware. table 11-1. configuration of a/d converter item configuration analog input 8 channels (ani0 to ani7) control registers a/d converter mode register 3 (adm3) analog input channel specification register 3 (ads3) power-fail comparison mode register 3 (pfm3) registers successive approximation register (sar) a/d conversion result register 3 (adcr3) power-fail comparison threshold value register 3 (pft3) 199 chapter 11 a/d converter user? manual u12790ej2v0ud figure 11-1. block diagram of a/d converter ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 sample & hold circuit av ss voltage comparator voltage comparator successive approximation register (sar) a/d conversion result register 3 (adcr3) controller controller av dd av ss adcs3 intad pfen3 adcs3 ads33 ads32 ads31 ads30 0 fr32 fr31 fr30 0 0 0 pfcm3 pfhrm3 power-fail comparison mode register 3 (pfm3) a/d converter mode register 3 (adm3) analog input channel specification register 3 (ads3) 4 internal bus selector tap selector power-fail comparison threshold value register 3 (pft3) 200 chapter 11 a/d converter user? manual u12790ej2v0ud (1) successive approximation register (sar) this register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (msb). when up to the least significant bit (lsb) is set (end of a/d conversion), the sar contents are transferred to the a/d conversion result register. (2) a/d conversion result register 3 (adcr3) this register holds the a/d conversion result. each time a/d conversion ends, the conversion result is loaded from the successive approximation register (sar). adcr is read by an 8-bit memory manipulation instruction. reset input makes adcr undefined. caution when data is written to a/d converter mode register 3 (adm3) and analog input channel specification register 3 (ads3), the contents of adcr3 are undefined. read the result of conversion after conversion has been completed and before writing data to adm3 and ads3. otherwise, the correct conversion result may not be read. (3) power-fail comparison threshold value register 3 (pft3) this register sets the threshold value to be compared with the value of a/d conversion result register 3 (adcr3). pft3 is read or written by using an 8-bit memory manipulation instruction. (4) sample & hold circuit the sample & hold circuit samples the input signal of the analog input pin selected by the selector when a/d conversion starts, and holds the sampled analog input voltage value during a/d conversion. (5) voltage comparator the voltage comparator compares the sampled analog input voltage to the series resistor string output voltage. (6) resistor string the resistor string is connected between av dd and av ss , and generates a voltage to be compared to the analog input. (7) ani0 to ani7 pins these are 8-channel analog input pins used to input analog signals to undergo a/d conversion to the a/d converter. cautions 1. use the ani0 to ani7 input voltages within the specified range. if a voltage of av dd or higher or av ss or lower is applied (even if within the absolute maximum ratings), the converted value of the corresponding channel becomes undefined and may adversely affect the converted values of other channels. 2. the analog input pins (ani0 to ani7) function alternately as input port pins (p10 to p17). when one of ani0 to ani7 is selected for a/d conversion, do not execute an input instruction to port 1; otherwise, the conversion resolution may drop. if a digital pulse is applied to a pin adjacent to the pin being a/d converted, the expected a/d conversion value may not be obtained due to coupling noise. do not apply a pulse to a pin adjacent to a pin being a/d converted. 201 chapter 11 a/d converter user s manual u12790ej2v0ud (8) av ss pin this is the ground pin of the a/d converter. always use this pin at the same voltage as gnd0, gnd1, gnd2, gndpll, and gndport even when the a/d converter is not used. (9) av dd pin this is the analog power supply pin of the a/d converter. always use this pin at the same voltage as v dd 0, v dd pll, and v dd port even when the a/d converter is not used. in the standby mode, the current flowing into the series resistor string can be reduced by stopping the conversion operation (by resetting bit 7 (adcs3) of a/d converter mode register 3 (adm3) to 0). 11.3 registers controlling a/d converter the following three registers control the a/d converter. a/d converter mode register 3 (adm3) analog input channel specification register 3 (ads3) power-fail comparison mode register 3 (pfm3) (1) a/d converter mode register 3 (adm3) this register selects the conversion time of the analog input to be converted and starts or stops the conversion operation. adm is set by a 1-bit or 8-bit memory manipulation instruction. this register is cleared to 00h after reset. 202 chapter 11 a/d converter user s manual u12790ej2v0ud figure 11-2. format of a/d converter mode register 3 (adm3) adcs3 control of a/d conversion operation 0 conversion operation stopped 1 conversion operation enabled fr32 fr31 fr30 selection of conversion time 0 0 0 288/f x (45.7 s) 0 0 1 240/f x (38.0 s) 0 1 0 192/f x (30.4 s) 1 0 0 144/f x (22.8 s) 1 0 1 120/f x (19.0 s) 1 1 0 96/f x (15.2 s) other than above setting prohibited cautions 1. the conversion result is undefined immediately after bit 7 (adcs3) is set to 1. 2. to change the data of bits 3 to 5 (fr30 to fr32), stop the a/d conversion operation. remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 6.3 mhz address ff12h symbol adm3 <7> adcs3 6 0 5 fr32 4 fr31 3 fr30 2 0 1 0 0 0 after reset 00h r/w r/w 203 chapter 11 a/d converter user s manual u12790ej2v0ud (2) analog input channel specification register 3 (ads3) this register specifies the input channel of the analog voltage to be converted. ads3 is set by an 8-bit memory manipulation instruction. the value of this register is cleared to 00h after reset. figure 11-3. format of analog input channel specification register 3 (ads3) ads33 ads32 ads31 ads30 specification of analog input channel 0000 ani0 0001 ani1 0010 ani2 0011 ani3 0100 ani4 0101 ani5 0110 ani6 0111 ani7 other than above setting prohibited address ff13h symbol ads3 6 0 7 0 5 0 4 0 3 ads33 2 ads32 1 ads31 0 ads30 after reset 00h r/w r/w 204 chapter 11 a/d converter user s manual u12790ej2v0ud (3) power-fail comparison mode register 3 (pfm3) pfm3 is set by a 1-bit or 8-bit memory manipulation instruction. the value of this register is initialized to 00h after reset. figure 11-4. format of power-fail comparison mode register 3 (pfm3) pfen3 power-fail comparison enable/disable 0 power-fail comparison disabled 1 power-fail comparison enabled pfcm3 selecttion of power-fail comparison mode 0 interrupt request (intad) generated when adcr3 pft 1 interrupt request (intad) generated when adcr3 < pft note pfhrm3 selection of power-fail halt repeat mode 0 power-fail halt repeat mode disabled 1 power-fail halt repeat mode disabled note when bit 5 (pfhrm3) is set to 1, power-fail comparison manipulation is enabled in the halt mode, which means that a/d conversion is repeated until an interrupt request (intad) is generated (this bit is reset to 0 when intad is generated). address ff16h symbol pfm3 <7> pfen3 <6> pfcm3 <5> pfhrm3 4 0 3 0 2 0 1 0 0 0 after reset 00h r/w r/w 205 chapter 11 a/d converter user s manual u12790ej2v0ud 11.4 a/d converter operations 11.4.1 basic operations of a/d converter (1) select one channel for a/d conversion using a/d converter analog input channel specification register 3 (ads3). (2) sample the voltage input to the selected analog input channel using the sample & hold circuit. (3) sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit holds the input analog voltage until the end of a/d conversion. (4) bit 7 of the successive approximation register (sar) is set and the tap selector sets the series resistor string voltage tap to (1/2) av dd . (5) the voltage difference between the series resistor string voltage tap and analog input is compared by a voltage comparator. if the analog input is greater than (1/2) av dd , the msb of sar remains set. if the input is smaller than (1/2) av dd , the msb is reset. (6) next, bit 6 of sar is automatically set and the operation proceeds to the next comparison. in this case, the series resistor string voltage tap is selected according to the preset value of bit 7 as described below. bit 7 = 1: (3/4) av dd bit 7 = 0: (1/4) av dd the voltage tap and analog input voltage are compared and bit 6 of sar is manipulated with the result as follows. analog input voltage voltage tap: bit 6 = 1 analog input voltage < voltage tap: bit 6 = 0 (7) comparison of this sort continues up to bit 0 of sar. (8) upon completion of the comparison of 8 bits, an effective digital resultant value remains in sar and the resultant value is transferred to and latched in a/d conversion result register 3 (adcr3). at the same time, the a/d conversion end interrupt request (intad) can also be generated. caution the value immediately after a/d conversion has been started is undefined. take appropriate measures, such as discarding the first conversion result by polling the a/d conversion end interrupt request (intad). 206 chapter 11 a/d converter user s manual u12790ej2v0ud figure 11-5. basic operation of a/d converter a/d conversion operations are performed continuously until bit 7 (adcs3) of adm is reset (0) by software. if a write to adm3 or ads3 is performed during an a/d conversion operation, the conversion operation is initialized, and if the adcs3 bit is set (1), conversion starts again from the beginning. the value of adcr3 is undefined after reset. sar adcr3 intad a/d converter operation sampling time sampling a /d conversion conversion time undefined 80h c0h or 40h conversion result conversion result 207 chapter 11 a/d converter user s manual u12790ej2v0ud 11.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and the a/d conversion result (the value stored in a/d conversion result register 3 (adcr3)) is shown by the following expression. adcr3 = int ( 256 + 0.5) or (adcr3 0.5) v in < (adcr3 + 0.5) where, int( ): function which returns integer part of value in parentheses. v in : analog input voltage av dd :av dd pin voltage adcr3: a/d conversion result register 3 (adcr3) value figure 11-6 shows the relationship between the analog input voltage and the a/d conversion result. figure 11-6. relationship between analog input voltage and a/d conversion result v in av dd av dd 256 av dd 256 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 255 254 253 3 2 1 0 a/d conversion results (adcr3) input voltage/av dd 208 chapter 11 a/d converter user s manual u12790ej2v0ud 11.4.3 a/d converter operating modes the a/d converter has the following two modes. a/d conversion mode: in this mode, the voltage applied to the analog input pin selected from ani0 to ani7 is converted into a digital signal. the result of the a/d conversion is stored in a/d conversion result register 3 (adcr3), and at the same time, an interrupt request signal (intad) is generated. power-fail comparison mode: the digital value resulting from a/d conversion is compared with the value assigned to power-fail comparison threshold value register 3 (pft3). if the result of the comparison matches the condition set by bit 6 (pfcm3) of power-fail comparison mode register 3 (pfm3), an interrupt request signal (intad) is generated. (1) a/d conversion operation mode when bit 7 (adcs3) of a/d converter mode register 3 (adm3) is set to 1, a/d conversion starts on the voltage applied to the analog input pins specified by bits 0 to 3 (ads30 to ads33) of ads3. at the end of the a/d conversion, the conversion result is stored in a/d conversion result register 3 (adcr3) and the interrupt request signal (intad) is generated. after one a/d conversion operation is started and ends, the next a/d conversion operation starts immediately. the a/d conversion operation con-tinues repeatedly until new data is written to adm3. if data is written to adcs3 again during a/d conversion, the converter suspends its a/d conversion operation and starts a/d conversion on the newly written data. if data with adcs3 set to 0 is written to adm3 during a/d conversion, the a/d conversion operation stops immediately. 209 chapter 11 a/d converter user s manual u12790ej2v0ud figure 11-7. a/d conversion operation remarks 1. n = 0, 1, ... , 7 2. m = 0, 1, ... , 7 note the conversion result is illegal immediately after bit 7 (adcs3) of a/d converter mode register 3 (adm3) has been set to 1 (to enable conversion). caution reset bit 5 (pfhrm3) of power-fail comparison mode register 3 (pfm3) to 0. conversion start adcs3 = 1 a /d conversion adcr3 intad (when pfen = 0) undefined note anin anim anin anim anim anin anin ads3 rewrite adm3 rewrite adcs3 = 0 conversion suspended conversion results are not stored stop stop 210 chapter 11 a/d converter user s manual u12790ej2v0ud (2) power-fail comparison mode in the power-fail comparison mode, the digital value converted from an analog input is compared in units of 8 bits. if the result of the comparison matches the condition set by bit 6 (pfcm3) of power-fail comparison mode register 3 (pfm3), an interrupt request (intad) is generated. note that the power-fail comparison mode can be used in the halt mode. at this time, the halt mode can be released by generating the interrupt request signal (intad) as a result of comparison (however, the a/d operation must be executed before the halt instruction is executed). to set the power-fail comparison mode, set bit 7 (pfen3) of pfm3 to 1, set bit 6 (pfcm3) to the generation condition of intad, and assign the threshold value to be compared with the value of a/d conversion result register 3 (adcr3) to power-fail comparison threshold value register 3 (pft3). by setting bit 7 (adcs3) of a/d converter mode register 3 (adm3) to 1, the voltage applied to the analog input pin specified by ads3 is converted into a digital signal. when a/d conversion has been completed, the result of the conversion is stored in adcr3. this conversion result is compared with the value set in pft3 and if the result of the comparison matches the condition set by bit 6 (pfcm3) of pfm3, an interrupt request signal (intad) is generated. figure 11-8. power-fail comparison threshold value register 3 (pft3) remark bit 7 (pft37) is the msb, and bit 0 (pft30) is the lsb. for the setting value, refer to 11.4.2 input voltage and conversion results . cautions 1. in the power-fail comparison mode, the first result (a/d conversion result and interrupt request (intad)) of the a/d conversion (started by setting bit 7 (adcs3) of a/d converter mode register 3 (adm3) to 1) is not correct. 2. when executing a/d conversion in the halt mode using the power-fail halt repeat mode, clear the interrupt request flag (adif) after the first conversion has been completed immediately after bit 7 (adcs3) of adm3 has been set to 1, and bit 5 (pfhrm3) of power- fail comparison mode register 3 (pfm3) has been set to 1, before executing the halt instruction. 3. to set the power-fail comparison mode in the halt mode, be sure to set bit 5 (pfhrm3) of pfm3 to 1 before executing the halt instruction. otherwise, comparison cannot be performed correctly because the conversion result in the halt mode is not stored in a/d conversion result register 3 (adcr3). if bit 5 (pfhrm3) of pfm3 is set in the normal operating mode (other than during halt operation), the a/d conversion is not performed correctly. therefore, be sure to clear this bit to 0 in the normal mode. symbol pft3 7 pft37 6 pft36 5 pft35 4 pft34 3 pft33 2 pft32 1 pft31 0 pft30 r/w r/w after reset 00h address ff15h 211 chapter 11 a/d converter user s manual u12790ej2v0ud figure 11-9. a/d conversion operation in power-fail comparison mode (1/3) (1) in normal mode (other than halt mode) notes 1. the conversion data is undefined immediately after bit 7 (adcs3) of a/d converter mode register 3 (adm3) is set to 1 (to start conversion). 2. the first result of a/d conversion (a/d conversion result and interrupt request) is not correct. do not use this result because there is a possibility that it will be determined that the comparison condition has matched even if it has not. caution set power-fail comparison threshold value register 3 (pft3) and power-fail comparison mode register 3 (pfm3) before starting conversion. be sure to reset bit 5 (pfhrm3) of pfm3 to 0 (to disable halt repeat mode setting). remark n = 0, 1, ... 7 m = 0, 1, ... 7 conversion starts adcs3 = 1 ads3 rewritten adm3 rewritten adcs3 = 0 a/d conversion adcr3 pft3, pfm3 set conversion stopped stop stop comparison condition does not match. note 2 comparison condition matches. anin anin anin anin anim anim unde- fined note 1 anin anin anim intad (when pfen3 = 1) comparison condition does not match. 212 chapter 11 a/d converter user s manual u12790ej2v0ud figure 11-9. a/d conversion operation in power-fail comparison mode (2/3) (2) in halt repeat mode (when generation of interrupt (intad) is used to release halt mode) notes 1. the conversion data is undefined immediately after bit 7 (adcs3) of a/d converter mode register 3 (adm3) is set to 1 (to start conversion). 2. when executing a/d conversion in the halt mode by using the power-fail comparison mode, clear the interrupt request flag (adif) after the first conversion has been completed immediately after bit 7 (adcs3) of adm3 has been set to 1, and bit 5 (pfhrm3) of power-fail comparison mode register 3 (pfm3) has been set to 1, before executing the halt instruction. 3. the first result of a/d conversion (a/d conversion result and interrupt request) is not correct. do not use this result because there is a possibility that it will be determined that the comparison condition has matched even if it has not. caution be sure to set bit 5 (pfhrm3) of pfm3 to 1 (to enable the halt repeat mode setting). remark n = 0, 1, ... 7 a/d conversion adcr3 stop stop comparison condition does not match. comparison condition does not match. note 3 comparison condition matches. comparison condition matches. (pfhrm3 is reset) anin anin anin anin anin anin unde- fined note 1 anin anin anin anin conversion starts adcs3 = 1 adif clear pfhrm3 = 1 adm3 rewritten adcs3 = 0 halt instruction note 2 halt operation interrupt request releases halt mode intad (when pfen3 = 1) pft3, pfm3 set 213 chapter 11 a/d converter user s manual u12790ej2v0ud figure 11-9. a/d conversion operation in power-fail comparison mode (3/3) (3) in halt repeat mode (when generation of interrupt (intad) is not used to release halt mode) notes 1. the conversion data is undefined immediately after bit 7 (adcs3) of a/d converter mode register 3 (adm3) is set to 1 (to start conversion). 2. when executing a/d conversion in the halt mode by using the power-fail halt repeat mode, clear the interrupt request flag (adif) after the first conversion has been completed immediately after bit 7 (adcs3) of adm3 has been set to 1, and bit 5 (pfhrm3) of power-fail comparison mode register 3 (pfm3) has been set to 1, before executing the halt instruction. 3. the first result of a/d conversion (a/d conversion result and interrupt request) is not correct. do not use this result because there is a possibility that it will be determined that the comparison condition has matched even if it has not. caution be sure to set bit 5 (pfhrm3) of pfm3 to 1 (to enable the halt repeat mode setting). remark n = 0, 1, ... 7 a/d conversion adcr3 stop comparison condition matches. (pfhrm3 is reset) anin anin anin anin anin unde- fined note 1 anin previous conversion result a/d conversion is in progress but conversion operation is stopped. previous conversion result ... conversion starts adcs3 = 1 adif clear pfhrm3 = 1 halt instruction note 2 halt operation interrupt request (intad) does not release halt mode intad (when pfen3 = 1) comparison condition does not match. note 3 ... pft3, pfm3 set 214 chapter 11 a/d converter user s manual u12790ej2v0ud 11.5 a/d converter cautions (1) current consumption in standby mode the a/d converter is stopped in the standby mode. at this time, the current consumption can be reduced by resetting bit 7 (adcs3) of a/d converter mode register 3 (adm3) to 0. figure 11-10 shows the circuit configuration of the series resistor string. figure 11-10. circuit configuration of series resistor string (2) input range of ani0 to ani7 the input voltages of ani0 to ani7 should be within the specification range. in particular, if a voltage of av dd or above or av ss or below is input (even if within the absolute maximum rating range), the conversion value for that channel will be undefined. the conversion values of the other channels may also be affected. (3) conflicting operations <1> conflict between writing a/d conversion result register 3 (adcr3) on completion of conversion and reading adcr3 by an instruction reading adcr3 takes precedence. after adcr3 has been read, a new conversion result is written to adcr3. <2> conflict between writing adcr3 on completion of conversion and writing a/d converter mode register 3 (adm3) or writing analog input channel specification register 3 (ads3) writing adm3 or ads3 takes precedence. adcr3 is not written. nor is the a/d conversion end interrupt request signal (intad) generated. av dd av ss p-ch series resistor string adcs3 215 chapter 11 a/d converter user s manual u12790ej2v0ud (4) noise countermeasures in order to maintain 8-bit resolution, attention must be paid to noise on the av dd and ani0 to ani7 pins. since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in figure 11-11 in order to reduce noise. figure 11-11. analog input pin handling (5) ani0/p10 to ani7/p17 pins the analog input pins ani0 to ani7 also function as i/o port pins (port 1). when a/d conversion is performed with any of pins ani0 to ani7 selected, be sure not to execute an instruction that inputs data to port 1 while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (6) input impedance of ani0 to ani7 pins in this a/d converter, the internal sampling capacitor is charged and sampling is performed for approx. one tenth of the conversion time. since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. to perform sufficient sampling, however, it is recommended to make the output impedance of the analog input source 10 k ? or lower, or attach a capacitor of around 100 pf to the ani0 to ani7 pins (see figure 11-11). ani0 to ani7 av dd analog voltage input c = 100 to 1,000 pf if there is possibility that noise whose level is av dd or higher or av ss or lower may enter, clamp with a diode with a small v f (0.3 v or less). v dd av ss v ss 216 chapter 11 a/d converter user s manual u12790ej2v0ud (7) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if analog input channel specification register 3 (ads3) is changed. caution is therefore required since, if the analog input pin is changed during a/d conversion, the a/d conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ads3 rewrite, and when adif is read immediately after the adm rewrite, adif may be set despite the fact that the a/d conversion for the post-change analog input has not ended. when a/d conversion is stopped and then resumed, clear the adif before it is resumed. figure 11-12. a/d conversion end interrupt request generation timing remarks 1. n = 0, 1, ..., 7 2. m = 0, 1, ..., 7 (8) conversion result immediately after starting a/d conversion the first a/d conversion result value is undefined immediately after an a/d conversion operation has been started. poll the a/d conversion end interrupt request (intad) and discard the first conversion result. (9) reading a/d conversion result register 3 (adcr3) if data is written to a/d converter mode register 3 (adm3) and analog input channel specification register 3 (ads3), the contents of adcr3 are undefined. read the conversion value before writing adm3 and ads3 after the conversion operation has been completed. otherwise, the correct conversion result may not be read. a /d conversion adcr3 intad anin anin anim anim anin anin anim anim adm3 rewrite (start of anin conversion) ads3 rewrite (start of anim conversion) adif is set but anim conversion has not ended 217 user? manual u12790ej2v0ud chapter 12 overview of serial interface the serial interface differs between the pd178096a and 178098a, and pd178076, 178078, and 178f098. table 12-1 shows the differences. table 12-1. differences between pd178096a and 178098a, and pd178076, 178078, and 178f098 item pd178096a, 178098a pd178076, 178078, 178f098 refer to: sio0 chapter 13 sio1 chapter 14 sio3 chapter 15 uart0 chapter 16 218 user? manual u12790ej2v0ud chapter 13 serial interface sio0 13.1 functions of serial interface sio0 serial interface sio0 employs the following five modes. operation stop mode 3-wire serial i/o mode sbi (serial bus interface) mode 2-wire serial i/o mode ? 2 c (inter ic) bus mode note note when using the i 2 c bus mode (including when this mode is implemented by software without using the internal hardware), consult nec electronics when placing an order for a mask. caution do not change the operation mode (3-wire serial i/o, sbi, 2-wire serial i/o, or i 2 c bus) while the operation of serial interface sio0 is enabled. to change the operation mode, stop the serial operation. (1) operation stop mode this mode is used when serial transfer is not carried out to reduce power consumption. (2) 3-wire serial i/o mode (msb-/lsb-first selectable) this mode is used for 8-bit data transfer using three lines, one each for the serial clock (sck0), serial output (so0) and serial input (si0). this mode enables simultaneous transmission/reception and therefore reduces the data transfer processing time. the start bit of transferred 8-bit data is switchable between the msb and lsb, so that devices can be connected regardless of their start bit recognition format. this mode should be used when connecting with peripheral i/o devices or display controllers which incorporate a conventional clocked serial interface as is the case with the 75xl, 78k, and 17k series. 219 chapter 13 serial interface sio0 user? manual u12790ej2v0ud (3) sbi (serial bus interface) mode (msb-first) this mode is used for 8-bit data transfer with two or more devices using two lines, one for the serial clock (sck0) and one for the serial data bus (sb0 or sb1). in the sbi mode, transfer data is classified into ?ddresses? ?ommands?and ?ata?for transmission/ reception, in conformance with serial bus format of nec electronics. ? address: data to select the target device for serial communication ? command: data to give instructions to the target device ? data: data actually transferred in fact, transfer is started when the master device outputs an ?ddress?to the serial bus to select one of the slave devices subject to communication. after that, ?ommands?and ?ata?are transmitted between the master device and slave device to implement serial communication. the receiver can automatically identify the received data as ?ddresses? ?ommands? or ?ata?by hardware. this function enables the i/o ports to be used effectively and the application program serial interface control portions to be simplified. in this mode, the wakeup function for handshake and the acknowledge and busy signal output function can also be used. figure 13-1. system configuration example of serial bus interface (sbi) master cpu sck0 sb0 sck0 sb0 slave cpu1 sck0 sb0 slave cpu2 sck0 sb0 slave cpun v dd 220 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (4) 2-wire serial i/o mode (msb-first) this mode is used for 8-bit data transfer using two lines, one for the serial clock (sck0) and one for the serial data bus (sb0 or sb1). this mode enables handling of any of the possible data transfer formats by controlling the sck0 level and the sb0 or sb1 output level. thus, the handshake line previously necessary for connection of two or more devices can be removed, resulting in an increased number of available i/o ports. (5) i 2 c bus mode (msb-first) this mode is used for 8-bit data transfer with two or more devices using two lines, one for the serial clock (scl) and one for the serial data bus (sda0 or sda1). this mode complies with the i 2 c bus format. in this mode, the transmitter outputs three kinds of data onto the serial data bus: start condition , data , and stop condition . the receiver automatically distinguishes the received data as start condition , data , or stop condition by hardware. figure 13-2. serial bus configuration example using i 2 c bus master cpu scl sda0 (sda1) scl sda0 (sda1) slave cpu 1 slave cpu 2 slave cpu n v dd v dd scl sda0 (sda1) scl sda0 (sda1) 221 chapter 13 serial interface sio0 user s manual u12790ej2v0ud 13.2 configuration of serial interface sio0 serial interface sio0 consists of the following hardware. table 13-1. configuration of serial interface sio0 item configuration registers serial i/o shift register 0 (sio0) slave address register 0 (sva0) control registers serial interface clock select register 0 (scl0) serial operating mode register 0 (csim0) serial bus interface control register 0 (sbic0) interrupt timing specification register 0 (sint0) port mode register 2 (pm2) port 2 (p2) 222 chapter 13 serial interface sio0 user s manual u12790ej2v0ud figure 13-3. block diagram of serial interface sio0 note example of operation in i 2 c bus mode. remark the output control selects between cmos output and n-ch open-drain output. csie0 coi wup csim 04 csim 03 csim 02 csim 01 csim 00 serial operating mode register 0 (csim0) controller output control selector si0/sb0/ sda0/p25 pm25 output control so0/sb1/ sda1/p26 pm26 output control sck0/ scl/p27 pm27 selector p25 output latch p26 output latch cld p27 output latch internal bus bsye ackd acke ackt cmdd reld cmdt relt internal bus stop condition/ start condition/ acknowledge detector serial clock counter serial clock controller clr d set q match acknowledge output circuit interrupt request signal generator ackd cmdd reld wup selector selector tcl33 tcl32 tcl31 tcl30 4 serial interface clock select register 0 (scl0) f x /2 2 -f x /2 9 intcsi0 cld sic svam bsye clc wrel wat1 wat0 csim01 1/16 divider csim01 interrupt timing specification register 0 (sint0) slave address register 0 (sva0) svam serial bus interface control register 0 (sbic0) 2 serial i/o shift register 0 (sio0) note note 223 chapter 13 serial interface sio0 user? manual u12790ej2v0ud (1) serial i/o shift register 0 (sio0) this is an 8-bit register used to carry out parallel/serial conversion and serial transmission/reception (shift operation) in synchronization with the serial clock. sio0 is set by an 8-bit memory manipulation instruction. when bit 7 (csie0) of serial operating mode register 0 (csim0) is 1, writing data to sio0 starts a serial operation. in transmission mode, data written to sio0 is output to the serial output (so0) or serial data bus (sb0/sb1). in reception mode, data is read from the serial input (si0) or sb0/sb1 to sio0. note that if the bus is driven in the sbi mode, 2-wire serial i/o mode, or i 2 c bus mode, the bus pins must serve for both input and output. thus, in the case of a device for reception, write ffh to sio0 in advance (except when address reception is carried out by setting bit 5 (wup) of csim0 to 1). in the i 2 c bus mode, set bit 7 (bsye) of serial bus interface control register 0 (sbic0) to 1. in the sbi mode, the busy state can be cleared by writing data to sio0. in this case, bit 7 (bsye) of serial bus interface control register 0 (sbic0) is not cleared to 0. reset input makes sio0 undefined. caution in the i 2 c bus mode, do not execute an instruction that writes to sio0 while wup (bit 5 of serial operating mode register 0 (csim0)) = 1. data can be received when the wakeup function is being used (wup = 1), even if such an instruction is not executed. for details of the wakeup function, refer to 13.4.5 (1) (c) wakeup function. (2) slave address register 0 (sva0) this is an 8-bit register to set the slave address value for connection of a slave device to the serial bus. sva0 is set by an 8-bit memory manipulation instruction. it is not used in the 3-wire serial i/o mode. the master device outputs a slave address for selection of a particular slave device to the connected slave devices. these two data (the slave address output from the master device and the sva0 value) are compared by an address comparator. if they match, that slave device has been selected. in this case, bit 6 (coi) of serial operating mode register 0 (csim0) becomes 1. the higher 7 bits of the slave address with the lsb masked can also be compared by setting the bit 4 (svam) of interrupt timing specification register 0 (sint0). if no match is detected in address reception, bit 2 (reld) of serial bus interface control register 0 (sbic0) is cleared to 0. by setting bit 5 (wup) of csim0 to 1 in the sbi mode, the wakeup function can be used. in this case, an interrupt request signal (intcsi0) is generated when the slave address output by the master matches the value of sva0 (the interrupt request is also generated when a stop condition is detected). this interrupt request indicates that the master has requested communication. further, when sva0 transmits data as a master or slave device in the sbi or 2-wire serial i/o mode, errors can be detected by using sva0. reset input makes sva0 undefined. 224 chapter 13 serial interface sio0 user? manual u12790ej2v0ud (3) so0 latch this latch holds the si0/sb0/sda0/p25 and so0/sb1/sda1/p26 pin levels. it can be directly controlled by software. in the sbi mode, this latch is set at the end of the 8th serial clock. (4) serial clock counter this counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received. (5) serial clock controller this circuit controls serial clock supply to serial i/o shift register 0 (sio0). when the internal system clock is used, this circuit also controls clock output to the sck0/scl/p27 pin. (6) interrupt request signal generator this circuit controls interrupt request signal generation. it generates an interrupt request signal in the following cases. in the 3-wire serial i/o mode and 2-wire serial i/o mode this circuit generates an interrupt request signal every eight serial clocks. in the sbi mode when wup note is 0 ........ generates an interrupt request signal every eight serial clocks. when wup note is 1 ........ generates an interrupt request signal when the serial i/o shift register 0 (sio0) value matches the slave address register 0 (sva0) value after address reception. note wup is the wakeup function specification bit. it is bit 5 of serial operating mode register 0 (csim0). in the i 2 c bus mode generates an interrupt request as shown in table 13-2. (7) output circuit and detector of control signals these two circuits output and detect various control signals in the sbi mode. they do not operate in the 3-wire serial i/o mode and 2-wire serial i/o mode. in the sbi mode busy/acknowledge output circuit, bus release/command/acknowledge detector in the i 2 c bus mode acknowledge output circuit, stop condition/start condition/acknowledge detector 225 chapter 13 serial interface sio0 user? manual u12790ej2v0ud table 13-2. serial interface sio0 interrupt request signal generation serial transfer mode bsye wup wat1 wat0 acke description i 2 c bus mode (transmit) 00100an interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait). normally, during transmission, the settings wat21, wat0=1, 0, are not used. they are used only when wanting to coordinate the receive time and processing systematically using software. ack information is generated by the receiving side, thus acke should be set to 0 (disabled). 1 1 0 an interrupt request signal is generated each time 9 serial clocks are counted (9-clock wait). ack information is generated by the receiving side, thus acke should be set to 0 (disabled). other than above setting prohibited i 2 c bus mode (receive) 10100an interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait). ack information is output by manipulating ackt by software after an interrupt is generated. 1 1 0/1 an interrupt request signal is generated each time 9 serial clocks are counted (9-clock wait). to automatically generate ack information, preset acke to 1 before transfer start. however, in the case of the master, set acke to 0 (disabled) before receiving the last data. 11111 after address is received, if the values of serial i/o shift register 0 (si00) and slave address register 0 (sva0) match, an interrupt request signal and a stop condition are generated. to automatically generate ack information, preset acke to 1 (enable) before transfer start. other than above setting prohibited remark bsye: bit 7 of the serial bus interface control register (sbic) acke: bit 5 of the serial bus interface control register (sbic) 226 chapter 13 serial interface sio0 user? manual u12790ej2v0ud 13.3 control registers of serial interface sio0 the following six registers are used to control serial interface sio0. serial interface clock select register 0 (scl0) serial operating mode register 0 (csim0) serial bus interface control register 0 (sbic0) interrupt timing specification register 0 (sint0) port mode register 2 (pm2) port 2 (1) serial interface clock select register 0 (scl0) this register sets the serial clock of serial interface sio0. scl0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets scl0 to 08h. figure 13-4. format of serial interface clock select register 0 (scl0) caution when rewriting scl0 to other data, stop the serial transfer operation first. remark f x : system clock oscillation frequency ( ): f x = 6.3 mhz selection of serial interface sio0 serial clock scl03 scl02 scl01 scl00 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 (setting prohibited) (788 khz) (394 khz) (197 khz) (98.4 khz) (49.2 khz) (24.6 khz) (12.3 khz) other than above setting prohibited 6543210 7 symbol scl0 0 0 0 0 scl03 scl02 scl01 scl00 ff43h 08h r/w address after reset r/w 227 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (2) serial operating mode register 0 (csim0) this register sets the serial interface sio0 serial clock, operating mode, operation enable/stop, and wakeup function, and displays the address comparator match signal. csim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. caution do not change the operating mode (3-wire serial i/o, 2-wire serial i/o, or sbi) while the operation of serial interface sio0 is enabled. to change the operating mode, stop the serial operation. figure 13-5. format of serial operating mode register 0 (csim0) (1/2) (continued) caution when using sck0 or scl, set p27 to 1. if p27 is set to 0, it always outputs a low level. notes 1. bit 6 (coi) is a read-only bit. 2. can be used as p25 (cmos input/output) when used only for transmission. 3. can be used freely as a port function. remark : don t care pm : port mode register p : output latch of port sbi mode <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 0 csim01 0 selection of serial interface sio0 clock input clock to sck0/scl/p27 pin from off-chip 0 0 sck0 (cmos i/o) r/w 1 clock specified by bits 0 to 3 of serial interface clock select register 0 (scl0) csim 04 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operating mode start bit sio/sb0/sda0/p25 pin function so0/sb1/sda1/p26 pin function sck0/scl/p27 pin function 10 0 0 0 0 0 0 1 1 note 3 note 3 note 3 note 3 msb p25 (cmos i/o) sb0 (n-ch open- drain i/o) sb1 (n-ch open- drain i/o) p26 (cmos i/o) 1 msb lsb 1 0001 note 2 3-wire serial l/o mode si0 note 2 (input) so0 (cmos output) sck0 (cmos i/o) 2-wire serial l/o mode or i 2 c bus mode 0 sck0/scl (n-ch open- drain i/o) 1 11 0 0 0 0 0 0 1 1 note 3 note 3 note 3 note 3 msb p25 (cmos i/o) sb0/sda0 (n-ch open- drain i/o) sb1/sda1 (n-ch open- drain i/o) p26 (cmos i/o) note 2 228 chapter 13 serial interface sio0 user? manual u12790ej2v0ud figure 13-5. format of serial operating mode register 0 (csim0) (2/2) notes 1. when using the wakeup function (wup = 1), set bit 5 (sic) of interrupt timing specification register 0 (sint0) as follows. do not execute a write instruction to serial i/o shift register 0 (sio0) while wup = 1. when the wakeup function is used in sbi mode: sic = 0 when the wakeup function is used in i 2 c bus mode: sic = 1 2. when csie0 = 0, coi is 0. wup 0 1 control of wake up function note 1 interrupt request signal generated with each serial transfer in any mode interrupt request signal generated when the address received after bus release (when cmdd = reld = 1) matches the slave address register 0 data in sbi mode r/w coi 0 1 slave address comparison result flag note 2 slave address register 0 and serial i/o shift register 0 data do not match slave address register 0 and serial i/o shift register 0 data match r csie0 0 1 control of serial interface sio0 operation operation stopped operation enabled r/w interrupt request signal generated when the address received after start condition detected (cmdd = 1) matches the slave address register 0 data in i 2 c bus mode 229 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (3) serial bus interface control register 0 (sbic0) this register sets the serial bus interface sio0 operation and display the status. sbic0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic0 to 00h. figure 13-6. format of serial bus interface control register 0 (sbic0) (1/3) note bits 2, 3, and 6 (reld, cmdd and ackd) are read-only bits. remarks 1. bits 0, 1, and 4 (reld, cmdt, and ackt) are 0 when read after data setting. 2. csie0: bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic0 bsye ackd acke ackt cmdd reld cmdt relt relt used for bus release signal output in sbi mode and stop condition signal output. when relt = 1, so iatch is set to 1. after so latch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w note address after reset r/w cmdt used for command signal output in sbi mode and start condition signal output. when cmdt = 1, so iatch is cleared to (0). after so latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w r reld detection of bus release (sbi mode)/stop condition (i 2 c bus mode) set conditions (reld =1) clear conditions (reld = 0) when bus release signal (rel) or stop condition is detected when transfer start instruction is executed if sio0 and sva0 values do not match in address reception when csie0 = 0 when reset input is applied r cmdd detection of command (sbi mode)/start condition (i 2 c bus mode) clear conditions (cmdd = 0) when transfer start instruction is executed when bus release signal (rel) or stop condition is detected when csie0 = 0 when reset input is applied set conditions (cmdd = 1) when command signal (cmd) or stop condition is detected 230 chapter 13 serial interface sio0 user s manual u12790ej2v0ud figure 13-6. format of serial bus interface control register 0 (sbic0) (2/3) (a) sbi mode note the busy mode can be canceled by the start of serial interface transfer or address signal reception. however, the bsye flag is not cleared to 0. remark csie0: bit 7 of serial operating mode register 0 (csim0) acke control of acknowledge signal output 0 acknowledge signal automatic output disabled (output with ackt enabled) the acknowledge signal is output in synchronization with the 9th falling edge of sck0 (automatically output when acke = 1). before completion of transfer the acknowledge signal is output in synchronization with the falling edge of sck0 just after execution of the instruction to be set to 1 (automatically output when acke = 1). however, not automatically cleared to 0 after acknowledge signal output. after completion of transfer 1 r/w r ackd detection of acknowledge clear conditions (ackd = 0) falling edge of sck0 immediately after the busy mode is released after executing the transfer start instruction when csie0 = 0 when reset input is applied set conditions (ackd = 1) when acknowledge signal (ack) is detected at the rising edge of sck0 clock after completion of transfer bsye synchronization of busy signal output control 0 busy signal output in synchronization with the falling edge of sck0 clock just after execution of the instruction to be cleared to 0 disabled. r/w note 1 busy signal output at the falling edge of sck0 clock following the acknowledge signal. ackt the acknowledge signal is output in synchronization with the falling edge of sck0 just after execution of the instruction to be set to 1, and after acknowledge signal output, automatically cleared to 0. used as acke = 0. also cleared to 0 upon start of serial interface transfer or when csie0 = 0. r/w 231 chapter 13 serial interface sio0 user s manual u12790ej2v0ud figure 13-6. format of serial bus interface control register 0 (sbic0) (3/3) (b) i 2 c bus mode notes 1. this setting should be performed before transfer. 2. if 8-clock wait mode is selected, the acknowledge signal at reception must be output using ackt. 3. the busy mode can be canceled by the start of serial interface transfer or the reception of an address signal. however, the bsye flag is not cleared to 0. 4. when using the wakeup function, be sure to set bsye to 1. remark csie0: bit 7 of serial operating mode register 0 (csim0) acke control of acknowledge signal output note 1 0 acknowledge signal automatic output disabled. (however, output with ackt is enabled) used for reception when 8-clock wait mode is selected or for transmission. note 2 acknowledge signal automatic output enabled. acknowledge signal output in synchronization with the falling edge of the 9th scl clock cycle (automatically output when acke = 1). however, not automatically cleared to 0 after acknowledge signal output. used in reception with 9-clock wait mode selected. 1 r/w r ackd detection of acknowledge clear conditions (ackd = 0) when transfer start instruction is executed when csie0 = 0 when reset input is applied set conditions (ackd = 1) when acknowledge signal (ack) is detected at the rising edge of scl clock after completion of transfer bsye control of n-ch open-drain output for transmission in i 2 c bus mode note 4 0 output enabled (transmission) r/w note 3 1 output disabled (reception) ackt sda0 (sda1) is set to low just after execution of the instruction to be set to 1 before the next scl falling edge. used for generating an ack signal by software if the 8-clock wait mode is selected. cleared to 0 if csie = 0 when a transfer by the serial interface is started. r/w 232 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (4) interrupt timing specification register 0 (sint0) this register sets the bus release interrupt and address mask functions and displays the p27/sck0/scl pin level status. sint0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets sint0 to 00h. figure 13-7. format of interrupt timing specification register 0 (sint0) (1/2) notes 1. bit 6 (cld) is a read-only bit. 2. when not using the i 2 c mode, set clc to 0. used in i 2 c bus mode. scl pin enters high-impedance state unless serial transfer is being performed (except for clock line, which is kept high). used to enable master device to generate start condition and stop condition signals. <6> <5> <4> <3> <2> 1 0 7 symbol sint0 0 cld sic svam clc wrel wat1 wat0 ff63h 00h r/w note 1 address after reset r/w wrel 0 wait state has already been cancelled. cancel wait state. automatically cleared to 0 when the state is cancelled. (used to cancel wait state by means of wat0 and wat1.) clc 0 1 control of clock level note 2 used in i 2 c bus mode. output level of scl pin made low unless serial transfer is being performed. r/w 1 control of wait sate cancellation r/w wat1 0 1 control of wait and interrupt interrupt servicing request generated at rising edge of 8th sck0 clock (keeping clock output in high impedance state). r/w wat0 0 0 used in i 2 c bus mode (8-clock wait). interrupt servicing request generated at rising edge of 8th scl clock. (in the case of a master device, scl output is made low to enter a wait state after 8 clock pulses are output. in the case of a slave device, scl output is made low to request a wait state after 8 clock pulses are input.) 1 1 used in i 2 c bus mode (9-clock wait). interrupt servicing request generated at rising edge of 9th scl clock . (in the case of a master device, scl output is made low to enter a wait state after 9 clock pulses are output. in the case of a slave device, scl output is made low to request a wait state after 9 clock pulses are input.) 0 setting prohibited 1 233 chapter 13 serial interface sio0 user? manual u12790ej2v0ud figure 13-7. format of interrupt timing specification register 0 (sint0) (2/2) notes 1. when using wakeup function in the i 2 c mode, set sic to 1. when using wakeup function in the sbi mode, set sic to 0. 2. when csie0 = 0, cld is 0. remark sva0: slave address register 0 csiif: interrupt request flag corresponding to intcsi0 csie0: bit 7 of serial operating mode register 0 (csim0) svam 0 1 sva0 bits to be used as slave address bits 0 to 7 bits 7 to 0 sic 0 selection of intcsi0 interrupt source note 1 csiif0 is set to 1 upon termination of serial interface sio0 transfer csiif0 is set to 1 upon bus release detection (sbi mode), stop condition detection (i 2 c bus mode), or termination of serial interface sio0 transfer cld 0 1 p27/sck0/scl pin level note 2 low level high level r/w r/w r 1 234 chapter 13 serial interface sio0 user s manual u12790ej2v0ud 13.4 operations of serial interface sio0 the following five operating modes are available for serial interface sio0. operation stop mode 3-wire serial i/o mode sbi mode 2-wire serial i/o mode i 2 c (inter ic) bus mode 13.4.1 operation stop mode serial transfer is not carried out in the operation stop mode. serial i/o shift register 0 (sio0) does not carry out shift operation either and thus it can be used as an ordinary 8-bit register. in the operation stop mode, the p25/si0/sb0/sda0, p26/so0/sb1/sda1 and p27/sck0/scl pins can be used as ordinary i/o ports. (1) register setting the operation stop mode is set using serial operating mode register 0 (csim0). csim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 0 ff60h 00h r/w address after reset r/w csie0 0 control of serial interface sio0 operation operation stopped operation enabled r/w 1 235 chapter 13 serial interface sio0 user s manual u12790ej2v0ud 13.4.2 3-wire serial i/o mode operation the 3-wire serial i/o mode is effective for connection of peripheral i/o units and display controllers which incorporate a conventional clocked serial interface as is the case with the 75xl, 78k, and 17k series. communication is carried out with three lines, one each for the serial clock (sck0), serial output (so0), and serial input (si0). (1) register setting the 3-wire serial i/o mode is set using serial operating mode register 0 (csim0), serial bus interface control register 0 (sbic0), port mode register 2 (pm2), and port 2 (p2). (a) serial operating mode register 0 (csim0) csim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. caution when using sck0 or scl, set p27 to 1. if p27 is set to 0, it always outputs a low level. notes 1. bit 6 (coi) is a read-only bit. 2. can be used as p25 (cmos i/o) when used only for transmission. 3. be sure to set wup to 0 when the 3-wire serial i/o mode is selected. remark : don t care pm : port mode register p : output latch of port <6><5>43210 <7> symbol csim0 csim01 0 selection of serial interface sio0 clock clock input to sck0/scl/p27 pin from off-chip 0 sbi mode (refer to 13.4.3 sbi mode operation ). r/w 1 clock specified by bits 0 to 3 of serial interface clock select register 0 (scl0) csim 04 0 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operating mode start bit sio/sb0/sda0/p25 pin function so0/sb1/sda1/p26 pin function sck0/scl/p27 pin function 10 wup 0 1 control of wakeup function interrupt request signal generated with each serial transfer in any mode setting prohibited note 3 r/w 1 msb lsb 1 0001 note 2 3-wire serial l/o mode si0 (input) so0 (cmos output) sck0 (cmos i/o) 2-wire serial i/o mode (refer to 13.4.4 2-wire serial i/o mode operation ) or i 2 c bus mode (refer to 13.4.5 i 2 c bus mode operation ). 11 note 2 note 2 csie0 0 control of serial interface sio0 operation operation stopped operation enabled r/w 1 csie0 coi wup csim04 csim03 csim02 csim01 0 236 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (b) serial bus interface control register 0 (sbic0) sbic0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic0 to 00h. remark csie0: bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic0 bsye ackd acke ackt cmdd reld cmdt relt relt when relt = 1, so iatch is set to 1. after so iatch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w address after reset r/w cmdt when cmdt = 1, so iatch is cleared to 0. after so latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w 237 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (2) communication operation the 3-wire serial i/o mode is used for data transmission/reception in 8-bit units. bit-wise data transmission/ reception is carried out in synchronization with the serial clock. the shift operation of serial i/o shift register 0 (sio0) is carried out at the falling edge of the serial clock (sck0). the transmitted data is held in the so0 latch and is output from the so0 pin. the received data input to the si0 pin is latched in sio0 at the rising edge of sck0. upon termination of 8-bit transfer, the sio0 operation stops automatically and the interrupt request flag (csiif0) is set. figure 13-8. 3-wire serial i/o mode timing the so0 pin is a cmos output pin and outputs the current so0 latch status. thus, the so0 pin output status can be manipulated by setting bit 0 (relt) and bit 1 (cmdt) of serial bus interface control register 0 (sbic0). however, do not carry out this manipulation during serial transfer. control the sck0 pin output level in the output mode (internal system clock mode) by manipulating the p27 output latch (refer to 13.4.8 sck0/scl/p27 pin output manipulation ). (3) other signals figure 13-9 shows the relt and cmdt operations. figure 13-9. relt and cmdt operations relt cmdt so0 latch si0 sck0 12345678 di7 di6 di5 di4 di3 di2 di1 di0 so0 do7 do6 do5 do4 do3 do2 do1 do0 csiif0 transfer start at falling edge of sck0 end of transfer 238 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (4) msb/lsb switching as the start bit in the 3-wire serial i/o mode, transfer can be selected to start from the msb or lsb. figure 13-10 shows the configuration of serial i/o shift register 0 (sio0) and the internal bus. as shown in the figure, msb/lsb can be read/written in reverse form. msb/lsb switching as the start bit can be specified by bit 2 (csim02) of serial operating mode register 0 (csim0). figure 13-10. circuit for switching transfer bit order start bit switching is realized by switching the bit order for data written to sio0. the sio0 shift order remains unchanged. thus, switching between msb-first and lsb-first must be performed before writing data to the shift register. (5) transfer start serial transfer is started by setting transfer data to serial i/o shift register 0 (sio0) when the following two conditions are satisfied. serial interface sio0 operation control bit (csie0) = 1. internal serial clock is stopped or sck0 is high level after 8-bit serial transfer. caution if csie0 is set to ??after writing data to sio0, transfer does not start. remark csie0: bit 7 of serial operating mode register 0 (csim0) upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. 7 6 internal bus 1 0 lsb-first msb-first read/write gate si0 shift register 0 (sio0) read/write gate so0 sck0 dq so0 latch 239 chapter 13 serial interface sio0 user s manual u12790ej2v0ud 13.4.3 sbi mode operation sbi (serial bus interface) is a high-speed serial interface that complies with the nec electronics serial bus format. sbi uses a single master device and employs the clocked serial i/o format with the addition of a bus configuration function. this function enables devices to communicate using only two lines. thus, when configuring a serial bus with two or more microcontrollers and peripheral ics, the number of ports to be used and the number of wires on the board can be decreased. the master device outputs three kinds of data to slave devices on the serial data bus: addresses to select the device to communicate with, commands to instruct the selected device, and data , which is the data actually sent. the slave device can identify the received data as address , command , or data by hardware. this function enables the application program that controls the serial interface sio0 to be simplified. the sbi function is incorporated into various devices including 75xl series and 78k series devices. figure 13-11 shows a serial bus configuration example when a cpu having a serial interface compliant with sbi and peripheral ics are used. in sbi, the sb0 (sb1) serial data bus pin is an open-drain output pin and therefore the serial data bus line behaves in the same way as a wired-and configuration. in addition, a pull-up resistor must be connected to the serial data bus line. when using the sbi mode, refer to (d) in (11) sbi mode cautions described later. figure 13-11. example of serial bus configuration with sbi caution when exchanging the master cpu/slave cpu, a pull-up resistor is necessary for the serial clock line (sck0) as well because serial clock line (sck0) i/o switching is carried out asynchronously between the master and slave cpus. master cpu sck0 sb0 (sb1) sck0 sb0 (sb1) sck0 sb0 (sb1) sck0 sb0 (sb1) slave cpu address 1 slave cpu address 2 slave ic address n serial clock serial data bus v dd 240 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (1) sbi functions in the conventional serial i/o format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary to provide chip select signals to identify commands and data, and to judge the busy state, because only the data transfer function is available. if these operations are to be controlled by software, the software will become heavily loaded. in sbi, a serial bus can be configured with two signal lines, one for the serial clock sck0 and one for the serial data bus sb0 (sb1). thus, use of sbi leads to a reduction in the number of microcontroller ports and the amount of wiring and routing on the board. the sbi functions are described below. (a) address/command/data identification function serial data is distinguished as addresses, commands, and data. (b) chip select function by address transmission the master executes slave chip selection by address transmission. (c) wakeup function the slave can easily judge address reception (chip select judgment) with the wakeup function (which can be set/reset by software). when the wakeup function is set, the interrupt request signal (intcsi0) is generated upon reception of a match address. thus, when communication is executed with two or more devices, the cpu of devices other than the selected slave device can operate independent of serial communications. (d) acknowledge signal (ack) control function the acknowledge signal is controlled to check serial data reception. (e) busy signal (busy) control function the busy signal is controlled to report the slave busy state. 241 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (2) sbi definition the sbi serial data format and the signals to be used are defined as follows. serial data to be transferred with sbi consists of three kinds of data: address , command , and data . figure 13-12 shows the address, command, and data transfer timing. figure 13-12. sbi transfer timing remark the dotted line indicates the ready status. the bus release signal and the command signal are output by the master device. busy is output by the slave device. ack can be output by either the master or slave device (normally, the 8-bit data receiver outputs ack). serial clocks continue to be output by the master device from 8-bit data transfer start to busy release. sck0 sb0 (sb1) sck0 sb0 (sb1) sck0 sb0 (sb1) 89 9 a7 a0 ack busy c7 c0 ack busy ready 89 d7 d0 ack busy ready address transfer command transfer data transfer bus release signal command signal address command data 242 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (a) bus release signal (rel) the bus release signal occurs when the sb0 (sb1) line changes from low level to high level when the sck0 line is high level (without serial clock output). this signal is output by the master device. figure 13-13. bus release signal the bus release signal indicates that the master device is going to transmit an address to the slave device. the slave device incorporates hardware to detect the bus release signal. caution a transition of the sb0 (sb1) pin from low to high is recognized as a bus release signal when the sck0 line is high. if the change timing of the bus is shifted due to the influence of board capacitance, data that is transmitted may be identified as a bus release signal by mistake. exercise care when wiring. (b) command signal (cmd) the command signal occurs when the sb0 (sb1) line changes from high level to low level when the sck0 line is high level (without serial clock output). this signal is output by the master device. figure 13-14. command signal the command signal indicates that the master is going to transmit a command to the slave (however, the command signal following the bus release signal indicates that an address is to be transmitted). the slave device incorporates hardware to detect the command signal. caution a transition of the sb0 (sb1) pin from high to low is recognized as a command signal when the sck0 line is high. if the change timing of the bus is shifted due to the influence of board capacitance, data that is transmitted may be identified as a command signal by mistake. exercise care when wiring. sck0 "h" sb0 (sb1) sck0 "h" sb0 (sb1) 243 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (c) address an address is 8-bit data that the master device outputs to the slave devices connected to the bus line in order to select a particular slave device. figure 13-15. addresses eight-bit data following the bus release and command signals is defined as an address . in the slave device, this condition is detected by hardware and whether or not the 8-bit data matches that slave s specification number (slave address) is checked by hardware. if the 8-bit data matches the slave address, that slave device has been selected. after that, communication with the master device continues until a release instruction is received from the master device. figure 13-16. slave selection by address master slave 1 not selected slave 2 selected slave 3 not selected slave 4 not selected slave 2 address transmission sck0 a7 a6 a5 a4 a3 a2 a1 a0 12345678 sb0 (sb1) address command signal bus release signal 244 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (d) command and data the master device transmits commands to and transmits/receives data to/from the slave device selected by address transmission. figure 13-17. commands figure 13-18. data eight-bit data following a command signal is defined as command data. eight-bit data without a command signal is defined as data . command and data operation procedures can be determined by the user according to their communication specifications. sck0 d7 d6 d5 d4 d3 d2 d1 d0 12345678 sb0 (sb1) data sck0 c7 c6 c5 c4 c3 c2 c1 c0 12345678 sb0 (sb1) command command signal 245 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (e) acknowledge signal (ack) the acknowledge signal is used to check serial data reception between the transmitter and receiver. figure 13-19. acknowledge signal [when output in synchronization with 11th sck0 clock] [when output in synchronization with 9th sck0 clock] the acknowledge signal is one-shot pulse generated at the falling edge of sck0 after 8-bit data transfer. it can be positioned anywhere and can be synchronized with any sck0 clock. after 8-bit data transmission, the transmitter checks whether the receiver has returned the acknowledge signal. if the acknowledge signal is not returned for the preset period of time after data transmission, it can be judged that data reception has not been carried out correctly. sck0 sb0 (sb1) 8 9 10 11 ack 89 ack sck0 sb0 (sb1) 246 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (f) busy signal (busy) and ready signal (ready) the busy signal is used to report to the master device that the slave device is not ready for data transmission/reception. the ready signal is intended to report to the master device that the slave device is ready for data transmission/reception. figure 13-20. busy and ready signals in sbi, the slave device notifies the master device of the busy state by setting the sb0 (sb1) line to the low level. busy signal output follows acknowledge signal output from the master or slave device. it is set/reset at the falling edge of sck0. when the busy signal is reset, the master device automatically terminates the output of the sck0 serial clock. when the busy signal is reset and the ready signal is set, the master device can start the next transfer. caution in the sbi mode, sbi outputs the busy signal after the busy clear instruction has been executed until the next serial clock falls. if wup is set to 1 by mistake during this period, busy will not be cleared. before setting wup to 1, therefore, clear busy, and make sure that the sb0 (sb1) pin has gone high. (3) register setting the sbi mode is set using serial operating mode register 0 (csim0), serial bus interface control register 0 (sbic0), interrupt timing specification register 0 (sint0), port mode register 2 (pm2), and port 2 (p2). (a) serial operating mode register 0 (csim0) csim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. ready ack sck0 sb0 (sb1) busy 89 247 chapter 13 serial interface sio0 user s manual u12790ej2v0ud caution when using sck0 or scl, set p27 to 1. if p27 is set to 0, it always outputs a low level. notes 1. bit 6 (coi) is a read-only bit. 2. can be used freely as a port. 3. clear bit 5 (sic) of interrupt timing specification register 0 (sint0) to 0 when using the wake- up function in the sbi mode (wup=1). 4. when csie0 = 0, coi is 0. remark : don t care pm : port mode register p : output latch of port sbi mode <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 0 csim01 0 selection of serial interface sio0 clock clock input to sck0/scl/p27 pin from off-chip 0 r/w 1 clock specified by bits 0 to 3 of serial interface clock select register 0 (scl0) csim 04 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operating mode start bit si0/sb0/sda0/p25 pin function so0/sb1/sda1/p26 pin function sck0/scl/p27 pin function 10 0 0 0 0 0 0 1 1 note 2 note 2 note 2 note 2 msb p25 (cmos i/o) sb0 (n-ch open- drain i/o) sb1 (n-ch open- drain i/o) p26 (cmos i/o) wup 0 1 control of wakeup function note 3 interrupt request signal generated with each serial transfer in any mode interrupt request signal generated when the address received after bus release (when cmdd = reld = 1) matches the slave address register 0 data in sbi mode r/w 11 3-wire serial i/o mode (refer to 13.4.2 3-wire serial i/o mode operation ). 2-wire serial i/o mode (refer to 13.4.4 2-wire serial i/o mode operation ) or i 2 c bus mode (refer to 13.4.5 i 2 c bus mode operation ). coi 0 slave address comparison result flag note 4 slave address register 0 and serial i/o shift register 0 data do not match slave address register 0 and serial i/o shift register 0 data match r 1 csie0 0 control of serial interface sio0 operation operation stopped operation enabled r/w 1 sck0 (cmos i/o) 248 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (b) serial bus interface control register 0 (sbic0) sbic0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic0 to 00h. (continued) note bits 2, 3, and 6 (reld, cmdd and ackd) are read-only bits. remarks 1. bits 0, 1, and 4 (relt, cmdt, and ackt) are 0 when read after data setting. 2. csie0: bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic0 bsye ackd acke ackt cmdd reld cmdt relt relt used for bus release signal output. when relt = 1, so iatch is set to (1). after so latch setting, automatically cleared to (0). also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w note address after reset r/w cmdt used for command signal output. when cmdt = 1, so iatch is cleared to (0). after so latch clearance, automatically cleared to (0). also cleared to 0 when csie0 = 0. r/w r reld detection of bus release set conditions (reld = 1) clear conditions (reld = 0) when bus release signal (rel) is detected when transfer start instruction is executed if sio0 and sva0 values do not match in address reception when csie0 = 0 when reset input is applied r cmdd detection of command clear conditions (cmdd = 0) when transfer start instruction is executed when bus release signal (rel) is detected when csie0 = 0 when reset input is applied set conditions (cmdd = 1) when command signal (cmd) is detected the acknowledge signal is output in synchronization with the falling edge of sck0 just after execution of the instruction to be set to (1) and, after acknowledge signal output, is automatically cleared to (0). used as acke = 0. also cleared to (0) upon start of serial interface transfer or when csie0 = 0. r/w acke control of acknowledge signal output 0 acknowledge signal automatic output disabled (output with ackt enabled) the acknowledge signal is output in synchronization with the 9th falling edge of sck0 (automatically output when acke = 1). before completion of transfer the acknowledge signal is output in synchronization with the falling edge of sck0 just after execution of the instruction to be set to 1 (automatically output when acke = 1). however, not automatically cleared to 0 after acknowledge signal output. after completion of transfer 1 r/w ackt 249 chapter 13 serial interface sio0 user s manual u12790ej2v0ud note busy mode can be cleared by the start of serial interface transfer. however, the bsye flag is not cleared to 0. remark csie0: bit 7 of serial operating mode register 0 (csim0) r ackd detection of acknowledge clear conditions (ackd = 0) when sck0 falls immediately after the busy mode is released after the transfer start instruction is executed. when csie0 = 0 when reset input is applied set conditions (ackd = 1) when the acknowledge signal (ack) is detected at the rising edge of the sck0 clock after completion of transfer bsye control of busy signal output synchronization 0 busy signal output in synchronization with the falling edge of sck0 clock just after execution of the instruction to be cleared to (0) (makes ready status) disabled. r/w note 1 busy signal output at the falling edge of sck0 clock following the acknowledge signal. 250 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (c) interrupt timing specification register 0 (sint0) sint0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets sint0 to 00h. notes 1. bit 6 (cld) is a read-only bit. 2. when using the wakeup function in the sbi mode, set sic to 0. 3. when csie0 = 0, cld is 0. caution be sure to set bits 0 to 3 to 0 when using sbi mode. remark sva0: slave address register 0 csiif: interrupt request flag corresponding to intcsi0 csie0: bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> 1 0 7 symbol sint0 0 cld sic svam clc wrel wat1 wat0 ff63h 00h r/w note 1 address after reset r/w svam 0 1 sva0 bits to be used as slave address bits 0 to 7 bits 7 to 0 sic 0 selection of intcsi0 interrupt source note 2 csiif0 is set upon termination of serial interface sio0 transfer csiif0 is set upon bus release detection or termination of serial interface sio0 transfer cld 0 1 sck0/scl/p27 pin level note 3 low level high level r/w r/w r 1 251 chapter 13 serial interface sio0 user? manual u12790ej2v0ud (4) signals figures 13-21 to 13-26 show the signals and flag operations in sbi. table 13-3 lists the signals in sbi. figure 13-21. relt, cmdt, reld, and cmdd operations (master) figure 13-22. reld and cmdd operations (slave) write ffh to sio0 (transfer start instruction) sio0 sck0 sb0 (sb1) reld cmdd transfer start instruction a7 a6 a1 a0 12 789 ready a7 a6 a1 a0 ack slave address when addresses match when addresses do not match sck0 sb0 (sb1) relt cmdt cmdd reld sio0 slave address write to sio0 (transfer start instruction) 252 chapter 13 serial interface sio0 user s manual u12790ej2v0ud figure 13-23. ackt operation caution do not set ackt before termination of transfer. sck0 6 sb0 (sb1) ackt 7 8 9 d2 d1 d0 ack when set during this period ack signal is output for a period of one clock just after setting 253 chapter 13 serial interface sio0 user s manual u12790ej2v0ud figure 13-24. acke operations (a) when acke = 1 upon completion of transfer (b) when set after completion of transfer (c) when acke = 0 upon completion of transfer (d) when ?cke = 1?period is short sb0 (sb1) acke 1 2 789 d7 d6 d2 d1 d0 ack when acke = 1 at this point ack signal is output at 9th clock sck0 sb0 (sb1) acke 7 89 d1 d0 ack 6 d2 if set during this period and acke = 1 at the falling edge of the next sck0 ack signal is output for a period of one clock just after setting sck0 sb0 (sb1) acke 1 2 789 d7 d6 d2 d1 d0 when acke = 0 at this point ack signal is not output sck0 sb0 (sb1) acke if set and cleared during this period and acke = 0 at the falling edge of sck0 ack signal is not output d2 d1 d0 sck0 254 chapter 13 serial interface sio0 user s manual u12790ej2v0ud figure 13-25. ackd operations (a) when ack signal is output at 9th clock of sck0 (b) when ack signal is output after 9th clock of sck0 (c) clear timing when transfer start is set during busy figure 13-26. bsye operation sck0 sb0 (sb1) bsye 7 89 ack 6 when bsye = 1 at this point busy if reset during this period and bsye = 0 at the falling edge of sck0 d2 d1 d0 sck0 sb0 (sb1) ackd 789 d1 d0 ack 6 d2 transfer start instruction sio0 transfer start sb0 (sb1) ackd ack 9 sio0 78 d1 6 d2 d0 transfer start instruction transfer start sck0 sck0 sb0 (sb1) ackd ack 9 transfer start instruction sio0 78 d1 6 d2 d0 d6 d7 busy 255 chapter 13 serial interface sio0 user? manual u12790ej2v0ud table 13-3. signals in sbi mode (1/2) timing chart definition signal name output device output condition effect on flag meaning of signal cmd signal is output to indicate that transmit data is an address. i) transmit data is an address after rel signal output. ii) rel signal is not output and trans- mit data is a command. low-level signal to be output to sb0 (sb1) during one-clock period of sck0 after completion of serial reception [synchronous busy signal] low-level signal to be output to sb0 (sb1) following acknowledge signal 1 bsye = 0 2 execution of instruction for data write to sio0 (transfer start instruction) master/ slave sb0 (sb1) rising edge when sck0 = 1 master bus release signal (rel) relt set reld set cmdd cleared cmdd set cmdt set master command signal (cmd) sb0 (sb1) falling edge when sck0 = 1 acknowledge signal (ack) 1 acke = 1 2 ackt set ackd set completion of reception slave busy signal (busy) bsye = 1 serial receive disabled because of processing serial receive enabled slave ready signal (ready) high-level signal to be output to sb0 (sb1) before serial transfer start and after completion of serial transfer [synchronous busy output] sck0 "h" sb0 (sb1) "h" sb0 (sb1) sck0 sck0 d0 ready sb0 (sb1) d0 ready sb0 (sb1) ack busy busy ack 9 256 chapter 13 serial interface sio0 user s manual u12790ej2v0ud timing chart definition signal name output device output condition effects on flag meaning of signal synchronous clock to output address/command/ data, ack signal, synchro- nous busy signal, etc. address/command/data are transferred with the first eight synchronous clocks. 8-bit data to be transferred in synchronization with sck0 after output of only cmd signal without rel signal output master numeric values to be processed by slave or master device serial clock (sck0) timing of signal output to serial data bus address value of slave device on the serial bus address (a7 to a0) 8-bit data to be transferred in synchronization with sck0 after output of rel and cmd signals master command (c7 to c0) instructions and messages to the slave device master/ slave data (d7 to d0) 8-bit data to be transferred in synchronization with sck0 without output of rel and cmd signals table 13-3. signals in sbi mode (2/2) when csie0 = 1, execution of instruction for data write to sio0 (serial transfer start instruction) note 2 notes 1. when wup = 0, csiif0 is set at the rising edge of the 9th clock of sck0. when wup = 1, an address is received. csiif0 is set only when the address matches the slave address register 0 (sva0) value. 2. in the busy state, transfer starts after the ready state is set. master csiif0 set (rising edge of 9th clock of sck0) note 1 sck0 sb0 (sb1) 1278910 sck0 sb0 (sb1) 1278 rel cmd sck0 sb0 (sb1) 1278 cmd sck0 sb0 (sb1) 1278 257 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (5) pin configuration the serial clock pin (sck0) and serial data bus pin sb0 (sb1) have the following configurations. (a) sck0 ............ serial clock i/o pin <1> master ... cmos and push-pull output <2> slave ...... schmitt input (b) sb0 (sb1) .... serial data i/o alternate-function pin both master and slave devices have an n-ch open-drain output and a schmitt input. because the serial data bus line has an n-ch open-drain output, an external pull-up resistor is necessary. figure 13-27. pin configuration caution because the n-ch open-drain output must be made high impedance when data is received, write ffh to sio0 in advance. the n-ch open-drain output can be made high impedance throughout transfer. however, when the wakeup function specification bit (wup) = 1, the n-ch open-drain output is always made high impedance. thus, it is not necessary to write ffh to sio0. si0 so0 si0 so0 (clock input) clock output master device clock input (clock output) serial clock sck0 sck0 r l serial data bus sb0 (sb1) sb0 (sb1) n-ch open drain n-ch open drain slave device 258 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (6) address match detection method in the sbi mode, a particular slave device is selected by address communication from the master device and communication is started. address match detection is executed by hardware. csiif0 is set in the wakeup state (wup = 1) only when the address transmitted from the master device matches the value set to slave address register 0 (sva0). cautions 1. slave selection/non-selection is detected by matching of the slave address received after bus release (reld = 1). for this match detection, the match interrupt request (intcsi0) of the address generated with wup = 1 is normally used. thus, execute selection/non-selection detection using the slave address when wup = 1. 2. when detecting selection/non-selection without using an interrupt request with wup = 0, do so by means of transmission/reception of a command preset by the program instead of using the address match detection method. (7) error detection in the sbi mode, the serial bus sb0 (sb1) status being transmitted is fetched into the destination device, that is, serial i/o shift register 0 (sio0). thus, transmit errors can be detected in the following way. (a) method of comparing sio0 data before transmission to that after transmission in this case, if two data differ from each other, a transmit error is judged to have occurred. (b) method of using slave address register 0 (sva0) transmit data is set to both sio0 and sva0 and is transmitted. after termination of transmission, the coi bit (match signal coming from the address comparator) of serial operating mode register 0 (csim0) is tested. if 1 , normal transmission is judged to have been carried out. if 0 , a transmit error is judged to have occurred. (8) communication operation in the sbi mode, the master device normally selects one slave device as the communication target from among two or more devices by outputting an address to the serial bus. after the communication target device has been determined, commands and data are transmitted/received and serial communication is realized between the master and slave device. figures 13-28 to 13-31 show the data communication timing charts. the shift operation of serial i/o shift register 0 (sio0) is carried out at the falling edge of the serial clock (sck0). transmit data is latched into the so0 latch and is output msb-first from the sb0/p25 or sb1/p26 pin. receive data input to the sb0 (or sb1) pin at the rising edge of sck0 is latched into sio0. 259 chapter 13 serial interface sio0 user? manual u12790ej2v0ud figure 13-28. address transmission from master device to slave device (wup = 1) 1 2 3 4 5 6 7 8 9 sck0 pin a7 a6 a5 a4 a3 a2 a1 a0 ack busy sb0 (sb1) pin program processing serial transmission csiif0 generation ackd set sck0 stop hardware operation wup 0 ackt set program processing cmdd set csiif0 generation ack output hardware operation cmdt set relt set cmdt set write to sio0 interrupt servicing (preparation for next serial transfer) master device processing (transmitter) transfer line slave device processing (receiver) cmdd clear cmdd set reld set serial reception busy output ready (when sva0 = sio0) address busy clear busy clear 260 chapter 13 serial interface sio0 user s manual u12790ej2v0ud figure 13-29. command transmission from master device to slave device 1 2 3 4 5 6 7 8 9 sck0 pin c7 c6 c5 c4 c3 c2 c1 c0 ack busy sb0 (sb1) pin program processing serial transmission csiif0 generation ackd set sck0 stop hardware operation ackt set program processing csiif0 generation ack output hardware operation cmdt set write to sio0 interrupt servicing (preparation for next serial transfer) master device processing (transmitter) transfer line slave device processing (receiver) cmdd set serial reception busy output ready command busy clear busy clear sio0 read command analysis 261 chapter 13 serial interface sio0 user s manual u12790ej2v0ud figure 13-30. data transmission from master device to slave device 1 2 3 4 5 6 7 8 9 sck0 pin d7 d6 d5 d4 d3 d2 d1 d0 ack busy sb0 (sb1) pin program processing serial transmission csiif0 generation ackd set sck0 stop hardware operation ackt set program processing csiif0 generation ack output hardware operation write to sio0 interrupt servicing (preparation for next serial transfer) master device processing (transmitter) transfer line slave device processing (receiver) serial reception busy output ready data busy clear busy clear sio0 read 262 chapter 13 serial interface sio0 user s manual u12790ej2v0ud figure 13-31. data transmission from slave device to master device 1 2 3 4 5 6 7 8 9 sck0 pin d7 d6 d5 d4 d3 d2 d1 d0 ack busy sb0 (sb1) pin program processing serial reception csiif0 generation ack output serial reception hardware operation program processing csiif0 generation ackd set hardware operation ffh write to sio0 master device processing (receiver) transfer line slave device processing (transmitter) serial transmission busy output ready data busy clear write to sio0 sck0 stop busy clear 12 ready busy d7 d6 ackt set sio0 read receive data processing ffh write to sio0 write to sio0 263 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (9) transfer start serial transfer is started by setting transfer data to serial i/o shift register 0 (sio0) when the following two conditions are satisfied. serial interface sio0 operation control bit (csie0) = 1 internal serial clock is stopped or sck0 is at high level after 8-bit serial transfer. cautions 1. if csie0 is set to ??after data is written to sio0, transfer does not start. 2. because the n-ch open-drain output must be made high impedance for data reception, write ffh to sio0 in advance. however, when the wakeup function specification bit (wup) = 1, the n-ch open-drain output is always made high impedance. thus, it is not necessary to write ffh to sio0. 3. if data is written to sio0 when the slave is busy, the data is not lost. when the busy state is cleared and the sb0 (or sb1) input is set to the high level (ready) state, transfer starts. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. be sure to set the pins used to input/output data after input of the reset signal and before serial transfer of 1 byte as follows. <1> set the output latches of p25 and p26 to 1. <2> set bit 0 (relt) of serial bus interface control register 0 (sbic0) to 1. <3> clear the output latches of p25 and p26, which were set to 1 above, to 0. 264 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (10) method used to judge busy state of a slave when the device is in the master mode, use the method below to judge whether the slave device is in the busy state or not. <1> detect acknowledge signal (ack) or interrupt request signal generation. <2> set the port mode register pm25 (or pm26) of the sb0/p25 (or sb1/p26) pin to the input mode. <3> read out the pin state (when the pin level is high, the ready state is set). after the detection of the ready state, set the port mode register to 0 and return to the output mode. (11) sbi mode cautions (a) slave selection/non-selection is detected by match detection of the slave address received after bus release (reld = 1). for this match detection, the match interrupt (intcsi0) of the address generated with wup = 1 is normally used. thus, execute selection/non-selection detection using the slave address when wup = 1. (b) when detecting selection/non-selection without using an interrupt with wup = 0, do so by means of transmission/reception of a command preset by the program instead of using the address match detection method. (c) in the sbi mode, sbi outputs the busy signal after the busy clear instruction has been executed until the next serial clock falls. if wup is set to 1 by mistake during this period, busy will not be cleared. before setting wup to 1, therefore, clear busy, and make sure that the sb0 (sb1) pin has gone high. (d) for pins which are to be used for data i/o, be sure to carry out the following settings before serial transfer of the 1st byte after reset input. <1> set the p25 and p26 output latches to 1. <2> set bit 0 (relt) of the serial bus control register to 1. <3> reset the p25 and p26 output latches from 1 to 0. (e) a transition of the sb0 (sb1) pin from low to high or high to low is recognized as a bus release signal or a command signal when the sck0 line is high. if the change timing of the bus is shifted due to the influence of board capacitance, data that is transmitted may be identified as a bus release signal or a command signal by mistake. exercise care when wiring. 265 chapter 13 serial interface sio0 user s manual u12790ej2v0ud 13.4.4 2-wire serial i/o mode operation the 2-wire serial i/o mode can cope with any communication format by program. communication is basically carried out with two lines, one for the serial clock (sck0) and one for serial data i/o (sb0 or sb1). figure 13-32. serial bus configuration example using 2-wire serial i/o mode (1) register setting the 2-wire serial i/o mode is set using serial operating mode register 0 (csim0), serial bus interface control register 0 (sbic0), interrupt timing specification register 0 (sint0), port mode register 2 (pm2), and port 2 (p2). (a) serial operating mode register 0 (csim0) csim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. master sck0 slave sb0 (sb1) sck0 sb0 (sb1) v dd v dd 266 chapter 13 serial interface sio0 user? manual u12790ej2v0ud caution when using sck0, set p27 to 1. if p27 is set to 0, it always outputs a low level. notes 1. bit 6 (coi) is a read-only bit. 2. can be used freely as a port. 3. be sure to set wup to 0 in the 2-wire serial i/o mode. 4. when csie0 = 0, coi is 0. remark : don? care pm : port mode register p : output latch of port <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 0 csim01 0 selection of serial interface sio0 clock selection clock input to sck0/scl/p27 pin from off-chip r/w 1 clock specified by bits 0 to 3 of serial interface clock select register 0 (scl0) csim 04 0 ff61h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operating mode start bit sio/sb0/sda0/p25 pin function so0/sb1/sda1/p26 pin function sck0/scl/p27 pin function 10 wup 0 1 control of wakeup function interrupt request signal generated with each serial transfer in any mode setting prohibited note 3 r/w 2-wire serial l/o mode or i 2 c bus mode (refer to 13.4.5 ) 0 1 11 0 0 0 0 0 0 1 1 note 2 note 2 note 2 note 2 msb p25 (cmos i/o) sb0/sda0 (n-ch open- drain i/o) sb1/sda1 (n-ch open- drain i/o) p26 (cmos i/o) 3-wire serial i/o mode (refer to 13.4.2 3-wire serial i/o mode operation ) sbi mode (refer to 13.4.3 sbi mode operation ) coi 0 slave address comparison result flag note 4 slave address register 0 and serial i/o shift register 0 data do not match slave address register 0 and serial i/o shift register 0 data match r 1 csie0 0 control of serial interface sio0 operation operation stopped operation enabled r/w 1 sck0/scl (n-ch open- drain i/o) 267 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (b) serial bus interface control register 0 (sbic0) sbic0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic0 to 00h. (c) interrupt timing specification register 0 (sint0) sint0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sint0 to 00h. caution be sure to set bits 0 to 3 to 0 when using in 2-wire serial i/o mode. notes 1. bit 6 (cld) is a read-only bit. 2. when csie0 = 0, cld is 0. remark csie0: bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic0 bsye ackd acke ackt cmdd reld cmdt relt relt when relt = 1, so iatch is set to 1. after so iatch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w address after reset r/w cmdt when cmdt = 1, so iatch is cleared to 0. after so latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w <6> <5> <4> <3> <2> 1 0 7 symbol sint0 0 cld sic clc wrel wat1 wat0 ff63h 00h r/w note 1 address after reset r/w cld 0 1 sck0/scl/p27 pin level note 2 low level high level r svam 268 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (2) communication operation the 2-wire serial i/o mode is used for data transmission/reception in 8-bit units. data transmission/reception is carried out bit-wise in synchronization with the serial clock. the shift operation of serial i/o shift register 0 (sio0) is carried out in synchronization with the falling edge of the serial clock (sck0). the transmit data is held in the so0 latch and is output from the sb0/p25 (or sb1/ p26) pin on an msb-first basis. the receive data input from the sb0 (or sb1) pin is latched into the shift register at the rising edge of sck0. upon termination of 8-bit transfer, the shift register operation stops automatically and the interrupt request flag (csiif0) is set. figure 13-33. 2-wire serial i/o mode timing the sb0 (or sb1) pin specified for the serial data bus is an n-ch open-drain i/o and thus it must be externally connected to a pull-up resistor. because it is necessary to make the n-ch open-drain output high impedance for data reception, write ffh to sio0 in advance. the sb0 (or sb1) pin generates the so0 latch status and thus the sb0 (or sb1) pin output status can be manipulated by setting bit 0 (relt) and bit 1 (cmdt) of serial bus interface control register 0 (sbic0). however, do not carry out this manipulation during serial transfer. control the sck0 pin output level in the output mode (internal system clock mode) by manipulating the p27 output latch (refer to 13.4.8 sck0/scl/p27 pin output manipulation ). 123 4 5 6 7 8 sck0 d7 d6 d5 d4 d3 d2 d1 d0 sb0 (sb1) csiif0 transfer start at falling edge of sck0 end of transfer 269 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (3) signals figure 13-34 shows the relt and cmdt operations. figure 13-34. relt and cmdt operations (4) transfer start serial transfer is started by setting transfer data to serial i/o shift register 0 (sio0) when the following two conditions are satisfied. serial interface sio0 operation control bit (csie0) = 1 internal serial clock is stopped or sck0 is at high level after 8-bit serial transfer. cautions 1. if csie0 is set to ??after data is written to sio0, transfer does not start. 2. because the n-ch open-drain output must be made high impedance for data reception, write ffh to sio0 in advance. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. (5) error detection in the 2-wire serial i/o mode, the serial bus sb0 (sb1) status being transmitted is fetched into the destination device, that is, serial i/o shift register 0 (sio0). thus, a transmit error can be detected in the following way. (a) method of comparing sio0 data before transmission to that after transmission in this case, if the two data differ from each other, a transmit error is judged to have occurred. (b) method of using slave address register 0 (sva0) transmit data is set to both sio0 and sva0 and is transmitted. after termination of transmission, the coi bit (match signal coming from the address comparator) of serial operating mode register 0 (csim0) is tested. if 1 , normal transmission is judged to have been carried out. if 0 , a transmit error is judged to have occurred. relt cmdt so0 latch 270 chapter 13 serial interface sio0 user s manual u12790ej2v0ud 13.4.5 i 2 c bus mode operation the i 2 c bus mode is provided for when communication operations are performed between a single master device and multiple slave devices. this mode configures a serial bus that includes only a single master device, and is based on the clocked serial i/o format with the addition of bus configuration functions, which allows the master device to communicate with a number of (slave) devices using only two lines: a serial clock (scl) line and a serial data bus (sda0 or sda1) line. consequently, when the user plans to configure a serial bus which includes multiple microcontrollers and peripheral devices, using this configuration results in reduction of the required number of port pins and on-board wiring. in the i 2 c bus specification, the master sends start condition, data, and stop condition signals to slave devices via the serial data bus, while slave devices automatically detect and distinguish the type of signals using the signal detection function incorporated as hardware. this simplifies i 2 c bus control sections in the application program. an example of a serial bus configuration is shown in figure 13-35. the system below is composed of cpus and peripheral ics having serial interface hardware that complies with the i 2 c bus specification. note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because n- ch open-drain outputs are used for the serial clock pin (scl) and the serial data bus pin (sda0 or sda1) on the i 2 c bus. the signals used in the i 2 c bus mode are described in table 13-4. figure 13-35. serial bus configuration example using i 2 c bus scl sda0 (sda1) scl sda0 (sda1) scl sda0 (sda1) scl sda slave ic slave cpu 2 slave cpu 1 master cpu v dd serial clock serial data bus v dd 271 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (1) i 2 c bus mode functions in the i 2 c bus mode, the following functions are available. (a) automatic identification of serial data slave devices automatically detect and identify start condition, data, and stop condition signals sent via the serial data bus. (b) chip selection by specifying device address the master device can select a specific slave device connected to the i 2 c bus and communicate with it by sending in advance the address data corresponding to the destination device. (c) wakeup function when the received address matches the value of slave address register 0 (sva0), the slave device internally generates an interrupt signal (also generated when a stop condition is detected). therefore, cpus other than the selected slave device on the i 2 c bus can perform independent operations during serial communication. (d) acknowledge signal (ack) control function the master device and a slave device send and receive acknowledge signals to confirm that serial communication has been executed normally. (e) wait signal (wait) control function when a slave device is preparing for data transmission or reception and requires more waiting time, the slave device outputs a wait signal on the bus to inform the master device of the wait status. (2) i 2 c bus definition this section describes the format of serial data communication and the functions of the signals used in the i 2 c bus mode. first, the transfer timing of the start condition, data, and stop condition signals, which are output onto the signal data bus of the i 2 c bus, is shown in figure 13-36. figure 13-36. i 2 c bus serial data transfer timing the start condition, slave address, and stop condition signals are output by the master. the acknowledge signal (ack) is output by either the master or the slave device (normally by the device which has received the 8-bit data that was sent). a serial clock (scl) is continuously supplied from the master device. 1-7 8 9 1-7 8 9 1-7 8 9 address r/w ack data ack data ack scl start condition sda0(sda1) stop condition 272 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (a) start condition when the sda0 (sda1) pin level is changed from high to low while the scl pin is high, this transition is recognized as the start condition signal. this start condition signal, which is created using the scl and sda0 (or sda1) pins, is output from the master device to slave devices to initiate a serial transfer. refer to 13.4.6 cautions on use of i 2 c bus mode , for details of the start condition output. the start condition signal is detected by hardware incorporated in slave devices. figure 13-37. start condition (b) address the 7 bits following the start condition signal are defined as an address. the 7-bit address data is output by the master device to specify a specific slave from among those connected to the bus line. each slave device on the bus line must therefore have a different address. therefore, after a slave device detects the start condition, it compares the 7-bit address data received and the data of slave address register 0 (sva0). after the comparison, only the slave device in which the data matches becomes the communication partner, and subsequently performs communication with the master device until the master device sends a start condition or stop condition signal. figure 13-38. address (c) transfer direction specification the 1 bit that follows the 7-bit address data sent from the master device, is defined as the transfer direction specification bit. if this bit is 0, it is the master device which will send data to the slave. if it is 1, it is the slave device which will send data to the master. figure 13-39. transfer direction specification h scl sda0 (sda1) 1234567 a6 a5 a4 a3 a2 a1 a0 r/w address scl sda0 (sda1) 234567 a6 a5 a4 a3 a2 a1 a0 r/w transfer direction specification scl 8 1 sda0 (sda1) 273 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (d) acknowledge signal (ack) the acknowledge signal indicates that the transferred serial data has definitely been received. this signal is used between the transmitting side and receiving side devices for confirmation of correct data transfer. in principle, the receiving side device returns an acknowledge signal to the transmitting device each time it receives 8-bit data. the only exception is when the receiving side is the master device and the 8-bit data is the last transfer data; the master device outputs no acknowledge signal in this case. the transmitting side that has transferred 8-bit data waits for the acknowledge signal which will be sent from the receiving side. if the transmitting side device receives the acknowledge signal, which means a successful data transfer, it proceeds to the next processing. if this signal is not sent back from the slave device, this means that the data sent has not been received by the slave device, and therefore the master device outputs a stop condition signal to terminate subsequent transmissions. figure 13-40. acknowledge signal (e) stop condition if the sda0 (sda1) pin level changes from low to high while the scl pin is high, this transition is defined as a stop condition signal. the stop condition signal is output from the master to the slave device to terminate a serial transfer. the stop condition signal is detected by hardware incorporated in the slave device. figure 13-41. stop condition 1 234567 a6 a5 a4 a3 a2 a1 a0 r/w scl sda0 (sda1) 9 8 ack h scl sda0 (sda1) 274 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (f) wait signal (wait) the wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. during the wait state, the slave device continues to output the wait signal by keeping the scl pin low to delay subsequent transfers. when the wait state is released, the master device can start the next transfer. for the releasing operation of slave devices, refer to 13.4.6 cautions on use of i 2 c bus mode . figure 13-42. wait signal (a) wait of 8 clock cycles (b) wait of 9 clock cycles scl of master device d2 d1 d0 ack d7 output by manipulating ackt 6789 1 3 24 d6 d5 d4 set to low because slave device drives low, though master device returns to hi-z state. no wait is inserted after 9th clock cycle (and before master device starts next transfer). scl of slave device scl sda0 (sda1) scl of master device set to low because slave device drives low, though master device returns to hi-z state. scl of slave device scl d2 d1 d0 ack d7 output based on the value set in acke in advance 6789 23 d6 d5 1 sda0 (sda1) 275 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (3) register setting the i 2 c mode is set by serial operating mode register 0 (csim0), serial bus interface control register 0 (sbic0), interrupt timing specification register 0 (sint0), port mode register 2 (pm2), and port 2 (p2). (a) serial operating mode register 0 (csim0) csim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. 276 chapter 13 serial interface sio0 user s manual u12790ej2v0ud r/w csim01 selection of serial interface sio0 clock 0 clock input from off-chip to sck0/scl/p27 pin 1 clock specified by bits 0 to 3 of serial interface clock select register 0 (scl0) r/w csim csim csim pm25 p25 pm26 p26 pm27 p27 operating start si0/sb0/sda0/ so0/sb1/sda1/ sck0/scl/p27 04 03 02 mode bit p25 pin function p26 pin function pin function 0 3-wire serial i/o mode (refer to 13.4.2 3-wire serial i/o mode operation ) 1 0 sbi mode (refer to 13.4.3 sbi mode operation ) 11 0 0 0 0 1 2-wire serial msb p25 sb1/sda1 sck0/scl note 2 note 2 i/o (refer to (cmos i/o) (n-ch open- (n-ch open- 13.4.4 ) or i 2 c drain i/o) drain i/o) 10 0 01 bus mode sb0/sda0 p26 note 2 note 2 (n-ch open- (cmos i/o) drain i/o) r/w wup control of wakeup function note 3 0 interrupt request signal generated with each serial transfer in any mode 1 in i 2 c bus mode, interrupt request signal is generated when the address data received after start condition detection (when cmdd = 1) matches the data in slave address register 0. r coi slave address comparison result flag note 4 0 slave address register 0 and serial i/o shift register 0 data do not match 1 slave address register 0 and serial i/o shift register 0 data match r/w csie0 control of serial interface sio0 operation 0 operation stopped 1 operation enabled caution when using scl, set p27 to 1. if p27 is set to 0, it always outputs a low level. notes 1. bit 6 (coi) is a read-only bit. 2. can be used freely as a port. 3. when using the wakeup function in the i 2 c bus mode (wup = 1), set bit 5 (sic) of interrupt timing specification register 0 (sint0) to 1. do not execute a write instruction to serial i/o shift register 0 (sio0) while wup = 1. 4. when csie0 = 0, coi is 0. remark : don t care pm : port mode register p : output latch of port <6><5>43210 <7> symbol csim0 ff60h 00h r/w note 1 address after reset r/w csie0 coi wup csim04 csim03 csim02 csim01 0 277 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (b) serial bus interface control register 0 (sbic0) sbic0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic0 to 00h. r/w relt use for stop condition signal output. when relt = 1, so latch is set to 1. after so latch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w cmdt use for start condition signal output. when cmdt = 1, so latch is cleared to 0. after clearing so latch, automatically cleared to 0. also cleared to 0 when csie0 = 0. r reld detection of stop condition clear conditions (reld = 0) setting conditions (reld = 1) when transfer start instruction is executed when stop condition is detected if sio0 and sva0 values do not match in address reception when csie0 = 0 when reset input is applied r cmdd detects start condition clear conditions (cmdd = 0) setting conditions (cmdd = 1) when transfer start instruction is executed when start condition is detected when stop condition is detected when csie0 = 0 when reset input is applied r/w ackt sda0 (sda1) is set to low level after the instruction to be set to 1 is executed (ackt = 1) before the next scl falling edge. used for generating an ack signal by software if the 8-clock wait mode is selected. cleared to 0 if csie = 0 when a transfer by the serial interface is started. (continued) note bits 2, 3, and 6 (reld, cmdd, ackd) are read-only bits. <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic0 bsye ackd acke ff61h 00h r/w note address after reset r/w ackt cmdd reld cmdt relt 278 chapter 13 serial interface sio0 user s manual u12790ej2v0ud r/w acke control of acknowledge signal automatic output note 1 0 disabled (with ackt enabled). used when receiving data in the 8-clock wait mode or when transmitting data. note 2 1 enabled. after completion of transfer, the acknowledge signal is output in synchronization with the 9th falling edge of the scl clock (automatically output when acke = 1). however, not automatically cleared to 0 after acknowledge signal output. used for reception when the 9-clock wait mode is selected. r ackd detection of acknowledge clear conditions (ackd = 0) set conditions (ackd = 1) when transfer start instruction is executed when acknowledge signal is detected at rising when csie0 = 0 edge of scl clock after completion of transfer when reset input is applied r/w bsye note 3 control of n-ch open-drain output for transmission in i 2 c bus mode note 4 0 output enabled (transmission) 1 output disabled (reception) notes 1. this setting must be performed prior to transfer start. 2. in the 8-clock wait mode, use ackt for output of the acknowledge signal after normal data reception. 3. the busy mode can be released by the start of a serial interface transfer or reception of an address signal. however, the bsye flag is not cleared. 4. when using the wakeup function, be sure to set bsye to 1. 279 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (c) interrupt timing specification register 0 (sint0) sint0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets sint0 to 00h. r/w wat1 wat0 control of wait and interrupt 0 0 setting prohibited note 2 01 1 0 used in i 2 c bus mode (8-clock wait) an interrupt servicing request is generated on the rise of the 8th scl clock cycle. (in the case of a master device, the scl pin is driven low after output of 8 clock cycles, to enter the wait state. in the case of a slave device, the scl pin is driven low after input of 8 clock cycles, to request the wait state.) 1 1 used in i 2 c bus mode (9-clock wait) an interrupt servicing request is generated on the rise of the 9th scl clock cycle. (in the case of a master device, the scl pin is driven low after output of 9 clock cycles, to enter the wait state. in the case of a slave device, the scl pin is driven low after input of 9 clock cycles, to request the wait state.) r/w wrel control of wait release 0 indicates that the wait state has been released. 1 release the wait state. automatically cleared to 0 after releasing the wait state. this bit is used to release the wait state set by means of wat0 and wat1. r/w clc control of clock level 0 used in i 2 c bus mode. in cases other than serial transfer, scl pin output is driven low. 1 used in i 2 c bus mode. in cases other than serial transfer, scl pin output is set to high impedance. (the clock line is held high.) used by the master device to generate the start condition and stop condition signals. r/w svam sva0 bits used as slave address 0 bits 0 to 7 1 bits 7 to 0 r/w sic selection of intcsi0 interrupt source note 3 0 csiif0 is set to 1 after end of serial interface sio0 transfer. 1 csiif0 is set to 1 after end of serial interface sio0 transfer or when stop condition is detected. r cld sck0/scl/p27 pin level note 4 0 low level 1 high level notes 1. bit 6 (cld) is read-only. 2. when the i 2 c bus mode is used, be sure to set wat0 and wat1 to 1 and 0, or 1 and 1, respectively. 3. when using the wakeup function in i 2 c mode, be sure to set sic to 1. 4. when csie0 = 0, cld is 0. remark sva0: slave address register 0 <6> <5> <4> <3> <2> 1 0 7 symbol sint0 0 cld sic ff63h 00h r/w note 1 address after reset r/w svam clc wrel wat1 wat0 280 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (4) signals a list of signals in the i 2 c bus mode is given in table 13-4. table 13-4. signals in i 2 c bus mode signal name description start condition definition: sda0 (sda1) falling edge when scl is high note 1 function: indicates that serial communication will start and subsequent data is address data. signaled by: master signaled when: cmdt is set. affected flag(s): cmdd (is set). stop condition definition: sda0 (sda1) rising edge when scl is high note 1 function: indicates end of serial transmission. signaled by: master signaled when: relt is set. affected flag(s): reld (is set) and cmdd (is cleared). acknowledge signal (ack) definition: low level of sda0 (sda1) pin during one scl clock cycle after serial reception function: indicates completion of reception of 1 byte. signaled by: master or slave signaled when: ackt is set with acke = 1. affected flag(s): ackd (is set). wait (wait) definition: low-level signal output to scl function: indicates state in which serial reception is not possible. signaled by: slave signaled when: wat1, wat0 = 1x. affected flag(s): none serial clock (scl) definition: synchronization clock for output of various signals function: serial communication synchronization signal. signaled by: master signaled when: note 2 affected flag(s): csiif0 note 3 address (a6 to a0) definition: 7-bit data synchronized with scl immediately after start condition signal function: indicates address value for specification of slave on serial bus. signaled by: master signaled when: note 2 affected flag(s): csiif0 note 3 transfer direction (r/w) definition: 1-bit data output in synchronization with scl after address output function: indicates whether data transmission or reception is to be performed. signaled by: master signaled when: note 2 affected flag(s): csiif0 note 3 data (d7 to d0) definition: 8-bit data synchronized with scl, not immediately after start condition function: contains data to be actually sent. signaled by: master or slave signaled when: note 2 affected flag(s): csiif0 note 3 notes 1. the level of the serial clock can be controlled by clc of interrupt timing specification register 0 (sint0). 2. an instruction to write data to sio0 is executed when csie0 = 1 (serial transfer start directive). in the wait state, the serial transfer operation will be started after the wait state is released. 3. if the 8-clock wait is selected when wup = 0, csiif0 is set at the rising edge of the 8th clock cycle of scl. if the 9-clock wait is selected when wup = 0, csiif0 is set at the rising edge of the 9th clock cycle of scl. if wup = 1, csiif0 is set when an address is received and the address matches the slave address register 0 (sva0) value, and when a stop condition is detected. 281 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (5) pin configuration the configurations of the serial clock pin (scl) and the serial data bus pin sda0 (sda1) are shown below. (a) scl serial clock i/o alternate-function pin. <1> master n-ch open-drain output <2> slave schmitt input (b) sda0 (sda1) serial data i/o alternate-function pin. uses n-ch open-drain output and schmitt-input buffers for both master and slave devices. note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because open- drain buffers are used for the serial clock pin (scl) and the serial data bus pin (sda0 or sda1) on the i 2 c bus. figure 13-43. pin configuration caution because it is necessary to make an n-ch open-drain output high impedance while data is being received, set bit 6 (bsye) of serial bus interface control register 0 (sbic0) to 1 in advance and write ffh to serial i/o shift register 0 (sio0). when the wakeup function is used (when bit 5 (wup) of serial the serial operating mode register 0 (csim0) is set), do not write ffh to sio0 before reception. the n-ch open-drain output is always high impedance even if ffh is not written to sio0. (6) address match detection method in the i 2 c mode, the master can select a specific slave device by sending slave address data. address match detection is performed automatically by the slave device hardware. a slave device address is compared with the slave address sent from the master device. if they match and the wakeup state (wup) bit is then 1, the interrupt request flag (csiif0) is set (it is also set when a stop condition is detected). when using the wakeup function (wup = 1), set sic to 1. caution whether a slave is selected or not depends on detection of match of the data (address) received after the start condition. to detect this match, an address match detection interrupt (intcsi0) that occurs when wup = 1, is normally used. therefore, to enable detection of whether a slave is selected or not, be sure that wup = 1. v dd v dd scl sda0 (sda1) master device clock output (clock input) data output data input slave devices (clock output) clock input data output data input scl sda0 (sda1) 282 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (7) error detection in the i 2 c bus mode, transmit error detection can be performed by the following methods because the serial bus sda0 (sda1) status during transmission is also taken into serial i/o shift register 0 (sio0) of the transmitting device. (a) comparison of sio0 data before and after transmission in this case, a transmit error is judged to have occurred if the two data values are different. (b) using the slave address register 0 (sva0) transmit data is set in sio0 and sva0 before transmission is performed. after transmission, the coi bit (match signal from the address comparator) of serial operating mode register 0 (csim0) is tested: "1" indicates normal transmission, and "0" indicates a transmit error. (8) communication operation in the i 2 c bus mode, the master selects the slave device communicate with from among multiple devices by outputting address data onto the serial bus. after the slave address data, the master sends the r/w bit, which indicates the data transfer direction, and starts serial communication with the selected slave device. data communication timing charts are shown in figures 13-44 and 13-45. in the transmitting device, serial i/o shift register 0 (sio0) shifts transmit data to the so latch in synchronization with the falling edge of the serial clock (scl), the so0 latch outputs the data on an msb-first basis from the sda0 or sda1 pin to the receiving device. in the receiving device, the data input from the sda0 or sda1 pin is taken into serial i/o shift register 0 (sio0) in synchronization with the rising edge of scl. 283 chapter 13 serial interface sio0 user s manual u12790ej2v0ud figure 13-44. data transmission from master to slave (both master and slave selected 9-clock wait) (1/3) (a) start condition to address l l l 1 a5 a4 a3 a2 a1 a0 w ack a6 2345678 d7 d6 d5 d4 d3 12345 9 l l l l l sio0 master device operation transfer line slave device operation sio0 h l l l l l l l h h h h sio0 ffh write sio0 coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 address data 284 chapter 13 serial interface sio0 user s manual u12790ej2v0ud figure 13-44. data transmission from master to slave (both master and slave selected 9-clock wait) (2/3) (b) data l l l l 1 d5 d4 d3 d2 d1 d0 ack d6 d7 2345678 d7 d6 d5 d4 d3 12345 9 l l l l l l l sio0 sio0 h l l l l l l l h h h h sio0 ffh sio0 ffh write sio0 coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 master device operation transfer line slave device operation data data 285 chapter 13 serial interface sio0 user s manual u12790ej2v0ud figure 13-44. data transmission from master to slave (both master and slave selected 9-clock wait) (3/3) (c) stop condition l l 1 d5 d4 d3 d2 d1 d0 ack d6 d7 2345678 a6 a5 a4 a3 1234 9 l l l l sio0 sio0 h l l l l h h h sio0 ffh write sio0 coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 sio0 ffh master device operation transfer line slave device operation address data 286 chapter 13 serial interface sio0 user s manual u12790ej2v0ud figure 13-45. data transmission from slave to master (both master and slave selected 9-clock wait) (1/3) (a) start condition to address l l l 1 a0 a1 a2 a3 a4 a5 a6 r ack 2345678 d6 d7 d5 d4 d3 2 1345 9 l l l sio0 sio0 ffh h l l l l l l l h h write sio0 coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 sio0 master device operation transfer line slave device operation address data 287 chapter 13 serial interface sio0 user s manual u12790ej2v0ud figure 13-45. data transmission from slave to master (both master and slave selected 9-clock wait) (2/3) (b) data l l l l h h l 1 d1 d0 d2 d3 d4 d5 d6 d7 ack 2345678 d6 d7 d5 d4 d3 2 1345 9 l l l sio0 ffh sio0 ffh h l l l l l l l l l l h h write sio0 coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 sio0 sio0 master device operation transfer line slave device operation data data 288 chapter 13 serial interface sio0 user s manual u12790ej2v0ud figure 13-45. data transmission from slave to master (both master and slave selected 9-clock wait) (3/3) (c) stop condition l l 1 d1 d0 d2 d3 d4 d5 d6 d7 nak 2345678 a6 a5 a4 a3 1234 9 l l sio0 ffh sio0 h l l l l l l h h write sio0 coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 sio0 master device operation transfer line slave device operation data address 289 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (9) start of transfer a serial transfer is started by setting transfer data in serial i/o shift register 0 (sio0) if the following two conditions are satisfied. the serial interface sio0 operation control bit (csie0) = 1. after an 8-bit serial transfer, the internal serial clock is stopped or scl is low. cautions 1. be sure to set csie0 to 1 before writing data to sio0. setting csie0 to 1 after writing data to sio0 will not start a transfer operation. 2. because the n-ch open-drain output must be made high impedance during data reception, set bit 7 (bsye) of serial bus interface control register 0 (sbic0) to 1 before writing ffh to sio0. when the wakeup function is used (when bit 5 (wup) of serial operating mode register 0 (csim0) is set), do not write ffh to sio0 before reception. the n-ch open-drain output is always high impedance even if ffh is not written to sio0 . 3. if data is written to sio0 while the slave is in the wait state, that data is held. the transfer is started when scl is output after the wait state is cleared. when an 8-bit data transfer ends, serial transfer is stopped automatically and the interrupt request flag (csiif0) is set. 290 chapter 13 serial interface sio0 user s manual u12790ej2v0ud 13.4.6 cautions on use of i 2 c bus mode (1) start condition output (master) the scl pin normally outputs a low-level signal when no serial clock is output. it is necessary to change the scl pin to high in order to output a start condition signal. set clc of interrupt timing specification register 0 (sint0) to 1 to drive the scl pin high. after setting clc, clear clc to 0 and return the scl pin to low. if clc remains 1, no serial clock is output. if it is the master device which outputs the start condition and stop condition signals, confirm that cld is set to 1 after setting clc to 1; a slave device may have set scl to low (wait state). figure 13-46. start condition output scl clc cmdt cld sda0 (sda1) 291 chapter 13 serial interface sio0 user s manual u12790ej2v0ud (2) slave wait release the slave wait release operation is performed by setting the wrel flag or executing an sio0 write instruction. if the slave sends data, the wait is immediately released by execution of an sio0 write instruction and the clock rises without the start transmission bit being output on the data line. therefore, as shown in figure 13- 47, data should be transmitted by manipulating the p27 output latch via the program. at this time, control the low-level width ("a" in figure 13-47) of the first serial clock at the timing used for setting the p27 output latch to 1 after execution of an sio0 write instruction. in addition, if the acknowledge signal from the master is not output (if data transmission from the slave is completed), set the wrel flag of sint0 to 1 and release the wait. if the slave receives data, after execution of an sio0 write instruction, it is not necessary to manipulate the p27 output latch because the data to be received has already been output on the data line even if the wait is released. for the timing of these operations, see figures 13-44 and 13-45. figure 13-47. slave wait release (transmission) (3) reception completion of slave during processing of reception completion by a slave device, confirm the statuses of cmdd and coi (if cmdd = 1). this procedure is necessary to use the wakeup function normally. if an uncertain amount of data is sent from the master device, the slave device cannot determine whether the start condition signal or the data will be sent from the master. this may disable use of the wakeup function. writing ffh to sio0 setting csiif0 setting ackd serial reception 9 a 23 a0 r/w ack d7 d6 d5 p27 output latch 1 setting csiif0 ack output serial transmission write data to sio0 p27 output latch 0 wait release software operation hardware operation scl software operation hardware operation transfer line master device operation slave device operation 1 sda0 (sda1) 292 chapter 13 serial interface sio0 user s manual u12790ej2v0ud 13.4.7 restrictions in using i 2 c bus mode the following restrictions must be observed when using the pd178078, 178098a subseries. restrictions when using as slave device in i 2 c bus mode devices: pd178076, 178078, 178096a, 178098a, 178f098 ie-178098-ns-em1 description: if the wakeup function is executed (by setting the wup flag (bit 5 of serial operating mode register 0 (csim0)) to 1) in the serial transfer status note , data between another slave device and the master is identified as an address. if that data matches the slave address of the pd178078, 178098a subseries, therefore, the pd178078, 178098a subseries participates in communication, destroying the communicated data. note the serial transfer status is the status after serial i/o shift register 0 (sio0) has been written until the interrupt request flag (csiif0) is set to 1 due to the end of serial transfer. preventive measures: the above problem can be avoided by modifying the program. before executing the wakeup function, execute the program shown below that clears the serial transfer status. when executing the wakeup function, do not write an instruction that writes to sio0. data can be received during execution of the wake- up function even if such an instruction is not executed. this program clears the serial transfer status. to clear the serial transfer status, serial interface sio0 must be stopped once (by clearing the csie0 flag (bit 7 of serial operating mode register 0 (csim0)) to 0). if serial interface sio0 is stopped in the i 2 c bus mode, however, the scl pin outputs a high level and sda0 (sda1) pin outputs a low level. consequently, communication of the i 2 c bus may be affected. therefore, this program makes the scl and sda0 (sda1) pins go into a high-impedance state to prevent the i 2 c bus from being affected. note that, in this example, the sda0 (/p25) pin is used as the serial data i/o pin. if the sda1 (/p26) pin is used as the serial data i/o pin, take p2.5 and pm2.5 in the program below as p2.6 and pm2.6. for the timing of each signal when this program is executed, refer to figure 13-44. 293 chapter 13 serial interface sio0 user s manual u12790ej2v0ud example of program for clearing serial transfer status set1 p2.5 ; (1) set1 pm2.5 ; (2) set1 pm2.7 ; (3) clr1 csie0 ; (4) set1 csie0 ; (5) set1 relt ; (6) clr1 pm2.7 ; (7) clr1 p2.5 ; (8) clr1 pm2.5 ; (9) (1) instruction (5) prevents the sda0 pin from outputting a low level when the i 2 c bus mode is restored. the sda0 pin goes into a high-impedance state. (2) instruction (4) sets the p25 (/sda0) pin in the input mode to prevent the sda0 line from being affected when the port mode is restored. the input mode is set when instruction (2) is executed. (3) instruction (4) sets the p27 (/scl) pin in the input mode to prevent the scl line from being affected when the port mode is restored. the input mode is set when instruction (3) is executed. (4) the mode is changed from the i 2 c bus mode to the port mode. (5) the mode is changed from the port mode to the i 2 c bus mode. (6) instruction (8) prevents the sda0 pin from outputting a low level. (7) because the p27 pin must be set in the output mode in the i 2 c bus mode, the p27 pin is set in the output mode. (8) because the output latch of the p25 pin must be set to 0 in the i 2 c bus mode, the output latch of the p25 pin is set to 0. (9) because the p25 pin must be set in the output mode in the i 2 c bus mode, the p25 pin is set in the output mode. remark relt: bit 0 of serial bus interface control register 0 (sbic0) 294 chapter 13 serial interface sio0 user s manual u12790ej2v0ud 13.4.8 sck0/scl/p27 pin output manipulation because the sck0/scl/p27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. p27 output latch manipulation enables any value of sck0/scl to be set by software. (the si0/sb0/sda0 and so0/sb1/sda1 pins are controlled by the relt and cmdt bits of sbic0.) the procedure for manipulating sck0/scl/p27 pin output is described below. (1) set serial operating mode register 0 (csim0) (the sck0/scl pin is enabled for serial operation in the output mode). sck0 = 1 and scl = 0 with serial transfer suspended. (2) manipulate the p27 output latch with a bit manipulation instruction. figure 13-48. sck0/scl/p27 pin configuration to internal circuit sck0/scl/p27 p27 output latch when csie0 = 1 and csim01 = 1 sck0/scl from serial clock controller 295 user? manual u12790ej2v0ud chapter 14 serial interface sio1 14.1 functions of serial interface sio1 serial interface sio1 employs the following three modes. operation stop mode 3-wire serial i/o mode 3-wire serial i/o mode with automatic transmit/receive function (1) operation stop mode this mode is used when serial transfer is not carried out to reduce power consumption. (2) 3-wire serial i/o mode (msb-/lsb-first selectable) this mode is used for 8-bit data transfer using three lines, one each for the serial clock (sck1), serial output (so1) and serial input (si1). the 3-wire serial i/o mode enables simultaneous transmission/reception and so decreases the data transfer processing time. since the start bit of 8-bit data to undergo serial transfer is switchable between msb and lsb, connection is enabled with either start bit device. the 3-wire serial i/o mode is effective for connection of peripheral i/o units and display controllers which incorporate a conventional clocked serial interface such as the 75xl, 78k and 17k series. (3) 3-wire serial i/o mode with automatic transmit/receive function (msb-/lsb-first selectable) this mode has an automatic transmit/receive function in addition to the functions in (2) above. the automatic transmit/receive function is used to transmit/receive data with a maximum of 32 bytes. this function enables the hardware to transmit/receive data to/from an osd (on screen display) device and a device with a built-in display controller/driver independently of the cpu, thus alleviating the software load. 296 chapter 14 serial interface sio1 user? manual u12790ej2v0ud 14.2 configuration of serial interface sio1 serial interface sio1 consists of the following hardware. table 14-1. configuration of serial interface sio1 item configuration registers serial i/o shift register 1 (sio1) automatic data transmit/receive address pointer (adtp) control registers serial operating mode register 1 (csim1) automatic data transmit/receive control register (adtc) automatic data transmit/receive interval specification register (adti) port mode register 2 (pm2) port 2 (p2) 297 chapter 14 serial interface sio1 user? manual u12790ej2v0ud figure 14-1. block diagram of serial interface sio1 internal bus ate si1/p20 so1/p21 pm21 busy/p24 pm23 stb/p23 sck1/p22 pm22 dir1 p21 output latch p23 output latch dir1 selector selector hand- shake arld serial clock counter p22 output latch csie1 lsck1 q r s clear sio1 write serial i/o shift register 1 (sio1) buffer ram automatic data transmit/receive address pointer (adtp) internal bus adti7 adti4 adti3 adti2 adti1 adti0 match 5-bit counter adti0 to adti4 re arld erce err trf strb busy1 busy0 selector trf csie1 dir1 ate lsck1 scl11 scl10 serial operating mode register 1 (csim1) intcsi1 f x /2 4 to f x /2 6 automatic data transmit/receive interval specification register (adti) automatic data transmit/ receive control register (adtc) selector 298 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (1) serial i/o shift register 1 (sio1) this is an 8-bit register used to carry out parallel/serial conversion and serial transmission/reception (shift operation) in synchronization with the serial clock. sio1 is set by an 8-bit memory manipulation instruction. when the value in bit 7 (csie1) of serial operating mode register 1 (csim1) is 1, writing data to sio1 starts a serial operation. in transmission, data written to sio1 is output to the serial output (so1). in reception, data is read from the serial input (si1) to sio1. reset input makes sio1 undefined. caution do not write data to sio1 while the automatic transmit/receive function is activated. (2) automatic data transmit/receive address pointer (adtp) this register stores the value of (transmit data byte 1) while the automatic transmit/receive function is activated. as data is transferred/received, it is automatically decremented. adtp is set by an 8-bit memory manipulation instruction. the higher 3 bits must be set to 0. reset input sets adtp to 00h. caution do not write data to adtp while the automatic transmit/receive function is activated. (3) serial clock counter this counter counts the serial clocks to be output and input during transmission/reception to check whether 8-bit data has been transmitted/received. 299 chapter 14 serial interface sio1 user s manual u12790ej2v0ud 14.3 control registers of serial interface sio1 the following five registers are used to control serial interface sio1. serial operating mode register 1 (csim1) automatic data transmit/receive control register (adtc) automatic data transmit/receive interval specification register (adti) port mode register 2 (pm2) port 2 (p2) (1) serial operating mode register 1 (csim1) this register sets the serial interface sio1 serial clock, operating mode, operation enable/stop and automatic transmit/receive operation enable/stop. csim1 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim1 to 00h. 300 chapter 14 serial interface sio1 user s manual u12790ej2v0ud figure 14-2. format of serial operating mode register 1 (csim1) csie1 enable/disable of operation of serial interface sio1 shift register operation serial counter port note 1 0 operation stopped cleared port function 1 operation enabled count operation enabled serial function + port function dir1 specification of first bit of serial transfer data 0 msb 1 lsb ate selection of operating mode of serial interface sio1 0 3-wire serial i/o mode 1 3-wire serial i/o mode with automatic transmit/receive function lsck1 chip enable control of sck1 pin 0 sck1 is used as port (p22) when csie1 = 0. sck1 is used for clock output when csie1 = 1. 1 sck1 is fixed to high level when csie1 = 0. sck1 is used for clock output when csie1 = 1. scl11 scl10 selection of serial clock of serial interface sio1 0 0 external clock input to sck1 pin note 2 01f x /2 4 (394 khz) 10f x /2 5 (197 khz) 11f x /2 6 (98.4 khz) notes 1. when csie1 = 0 (sio1 operation stop status), the p20/si1, p21/so1, p22/sck1, p23/stb, and p24/busy pins can be used as port pins. 2. when external clock input is selected by clearing scl11 and scl10 to 0, 0, clear bits 2 (strb) and 1 (busy1) of the automatic data transmit/receive control register (adtc) to 0, 0. remark ( ): f x = 6.3 mhz <7> csie1 6 dir1 <5> ate 4 lsck1 3 0 2 0 1 scl11 0 scl10 symbol csim1 r/w r/w after reset 00h address ff68h 301 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (2) automatic data transmit/receive control register (adtc) this register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable and displays automatic transmit/receive execution. adtc is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets adtc to 00h. figure 14-3. format of automatic data transmit/receive control register (adtc) <6> <5> <4> <3> <2> <1> <0> <7> symbol adtc re arld erce err trf strb busy1 busy0 ff6ah 00h r/w note 1 address after reset r/w busy1 0 1 1 control of busy input not using busy input note 2 busy input enabled (active high) busy input enabled (active low) busy0 0 1 strb 0 1 control of strobe output strobe output disabled note 3 strobe output enabled trf 1 status of automatic transmit/receive function note 4 end of automatic transmission/reception detected. (this bit is set to 0 upon suspension of automatic transmission/reception or when arld = 0.) automatic transmission/reception in progress. (this bit is set to 1 when data is written to sio1.) r/w r/w r r err 0 1 error detection of automatic transmit/receive function no error (this bit is set to 0 when data is written to sio1.) error occurred r/w arld 0 1 operating mode selection of automatic transmit/ receive function single operating mode repetitive operating mode r/w re 0 1 receive control of automatic transmit/receive function receive disabled note 5 receive enabled r/w erce 0 error check control of automatic transmit/ receive function error check disabled error check enabled (only when busy1 = 1) 0 1 302 chapter 14 serial interface sio1 user s manual u12790ej2v0ud notes 1. bits 3 and 4 (trf and err) are read-only bits. 2. when busy1 is reset to 0, p24 (cmos i/o) is used even when bit 7 (csie1) of serial operating mode register 1 (csim1) is set to 1. 3. when strb is reset to 0, p23 (cmos i/o) is used even when bit 7 (csie1) of csim1 is set to 1. 4. when an interrupt is acknowledged, interrupt request flag csiif1 is cleared. therefore, use trf, instead of csiif1, to identify the completion of automatic transmission/reception. 5. when re is reset to 0, p20 (cmos i/o) is used even when bit 7 (csie1) of csim1 is set to 1. caution when an external clock input is selected with bits 0 and 1 (scl11 and scl10) of csim1 set to 0, set bits 2 and 1 (strb and busy1) of adtc to 0, 0. remark : don't care 303 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (3) automatic data transmit/receive interval specification register (adti) this register sets the automatic data transmit/receive function data transfer interval. adti is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets adti to 00h. figure 14-4. format of automatic data transmit/receive interval specification register (adti) (1/2) control of data transfer interval (f x = 6.3 mhz, f sck = 394 khz) note 2 adti4 adti3 adti2 adti1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 5.08 s + 0.5/f sck 7.61 s + 0.5/f sck 10.2 s + 0.5/f sck 12.7 s + 0.5/f sck 15.2 s + 0.5/f sck 17.8 s + 0.5/f sck 20.3 s + 0.5/f sck 22.8 s + 0.5/f sck 25.4 s + 0.5/f sck 27.9 s + 0.5/f sck 30.5 s + 0.5/f sck 33.0 s + 0.5/f sck 35.5 s + 0.5/f sck 38.1 s + 0.5/f sck 40.6 s + 0.5/f sck 6543210 7 symbol adti (continued) adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti7 0 control of data transfer interval no control of interval by adti note 1 control of interval by adti (adti0 to adti4) 1 adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 304 chapter 14 serial interface sio1 user s manual u12790ej2v0ud figure 14-4. format of automatic data transmit/receive interval specification register (adti) (2/2) notes 1. the interval time is 2/f sck . 2. the data transfer interval time is found from the following expressions (n: value set to adti0 to adti4). <1> n = 0 interval time = 2 + 0.5 f sck f sck <2> n = 1 to 31 interval time = n+1 + 0.5 f sck f sck cautions 1. do not write adti during operation of the automatic data transmit/receive function. 2. be sure to set bits 5 and 6 to 0. 3. when controlling the interval time of automatic transmit/receive data transfer by using adti, busy control is invalid. (refer to 14.4.3 (4) (a) busy control option.) remark f x : system clock oscillation frequency f sck : serial clock frequency specification of data transfer interval (f x = 6.3 mhz, f sck = 394 khz) note adti4 adti3 adti2 adti1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 43.1 s + 0.5/f sck 45.7 s + 0.5/f sck 48.2 s + 0.5/f sck 50.8 s + 0.5/f sck 53.3 s + 0.5/f sck 55.8 s + 0.5/f sck 58.4 s + 0.5/f sck 60.9 s + 0.5/f sck 63.5 s + 0.5/f sck 66.0 s + 0.5/f sck 68.5 s + 0.5/f sck 71.1 s + 0.5/f sck 73.6 s + 0.5/f sck 76.1 s + 0.5/f sck 78.6 s + 0.5/f sck 81.2 s + 0.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 305 chapter 14 serial interface sio1 user? manual u12790ej2v0ud (4) port mode register 2 (pm2) pm2 is a register that sets input/output of port 2 in 1-bit units. when using the p21/so1 pin as a serial data output, set pm21 and the output latch of p21 to 0. when using the p22/sck1 pin as a clock output, set pm22 and the output latch of p22 to 0. when using the p25/stb pin as a strobe output, set pm25 and the output latch of p25 to 0. when using the p20/si1 pin as a serial data input, the p22/sck1 pin as a clock input, and the p24/busy pin as a busy input, set pm20, pm22, and pm24 to 1. at this time, the output latches of p20, p22, and p24 can be either 0 or 1. pm2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets the value of pm2 to ffh. figure 14-5. format of port mode register 2 (pm2) address: ff22h after reset: ffh r/w symbol 76543210 pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2n i/o mode selection of p2n pin (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 306 chapter 14 serial interface sio1 user? manual u12790ej2v0ud 14.4 operations of serial interface sio1 the following three operating modes are available for serial interface sio1. operation stop mode 3-wire serial i/o mode 3-wire serial i/o mode with automatic transmit/receive function 14.4.1 operation stop mode serial transfer is not carried out in the operation stop mode. serial i/o shift register 1 (sio1) does not carry out shift operations either, and thus it can be used as an ordinary 8-bit register. in the operation stop mode, the p20/si1, p21/so1, p22/sck1, p23/stb and p24/busy pins can be used as ordinary i/o ports. (1) register setting the operation stop mode is set using serial operating mode register 1 (csim1). csim1 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim1 to 00h. csie1 enable/disable of operation of serial interface sio1 shift register operation serial counter port note 1 0 operation stopped cleared port function 1 operation enabled count operation enabled serial function + port function note when csie1 = 0 (sio1 operation stop status), the p20/si1, p21/so1, p22/sck1, p23/stb, and p24/ busy pins can be used as port pins. <7> csie1 6 dir1 <5> ate 4 lsck1 3 0 2 0 1 scl11 0 scl10 symbol csim1 r/w r/w after reset 00h address ff68h 307 chapter 14 serial interface sio1 user? manual u12790ej2v0ud 14.4.2 3-wire serial i/o mode operation the 3-wire serial i/o mode is effective for connection of peripheral i/o units and display controllers that incorporate a conventional synchronous serial interface such as the 75xl, 78k and 17k series. communication is carried out with three lines, one each for the serial clock (sck1), serial output (so1), and serial input (si1). (1) register setting the 3-wire serial i/o mode is set using serial operating mode register 1 (csim1), port mode register 2 (pm2), and port 2 (p2). (a) serial operating mode register 1 (csim1) csim1 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim1 to 00h. csie1 enable/disable of operation of serial interface sio1 shift register operation serial counter port note 1 0 operation stopped cleared port function 1 operation enabled count operation enabled serial function + port function dir1 start bit 0 msb 1 lsb ate selection of operating mode of serial interface sio1 0 3-wire serial i/o mode 1 3-wire serial i/o mode with automatic transmit/receive function lsck1 chip enable control of sck1 pin 0 sck1 is used as port (p22) when csie1 = 0. sck1 is used for clock output when csie1 = 1. 1 sck1 is fixed to high level when csie1 = 0. sck1 is used for clock output when csie1 = 1. scl11 scl10 selection of serial clock of serial interface sio1 0 0 external clock input to sck1 pin note 2 01f x /2 4 (394 khz) 10f x /2 5 (197 khz) 11f x /2 6 (98.4 khz) <7> csie1 6 dir1 <5> ate 4 lsck1 3 0 2 0 1 scl11 0 scl10 symbol csim1 r/w r/w after reset 00h address ff68h 308 chapter 14 serial interface sio1 user s manual u12790ej2v0ud notes 1. when csie1 = 0 (sio1 operation stop status), the p20/si1, p21/so1, p22/sck1, p23/stb, and p24/busy pins can be used as port pins. 2. when external clock input is selected by clearing scl11 and scl10 to 0, 0, clear bits 2 (strb) and 1 (busy1) of the automatic data transmit/receive control register (adtc) to 0, 0. remark ( ) : f x = 6.3 mhz (b) port mode register 2 (pm2) pm2 is a register that sets input/output of port 2 in 1-bit units. when using the p21/so1 pin as a serial data output, set pm21 and the output latch of p21 to 0. when using the p22/sck1 pin as a clock output, set pm22 and the output latch of p22 to 0. when using the p25/stb pin as a strobe output, set pm25 and the output latch of p25 to 0. when using the p20/si1 pin as a serial data input, the p22/sck1 pin as a clock input, and the p24/busy pin as a busy input, set pm20, pm22, and pm24 to 1. at this time, the output latches of p20, p22, and p24 can be either 0 or 1. pm2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets the value of pm2 to ffh. address: ff22h after reset: ffh r/w symbol 76543210 pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2n i/o mode selection of p2n pin (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 309 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (2) communication operation the 3-wire serial i/o mode is used for data transmission/reception in 8-bit units. bit-wise data transmission/ reception is carried out in synchronization with the serial clock. the shift operation of serial i/o shift register 1 (sio1) is carried out at the falling edge of the serial clock (sck1). the transmit data is held in the so1 latch and is output from the so1 pin. the receive data input to the si1 pin is latched into sio1 at the rising edge of sck1. upon termination of 8-bit transfer, the sio1 operation stops automatically and the interrupt request flag (csiif1) is set. figure 14-6. 3-wire serial i/o mode timing caution the so1 pin becomes low level by sio1 write. si1 sck1 12345678 di7 di6 di5 di4 di3 di2 di1 di0 so1 do7 do6 do5 do4 do3 do2 do1 do0 csiif1 transfer start at falling edge of sck1 end of transfer sio1 write 310 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (3) msb/lsb switching as the start bit in the 3-wire serial i/o mode, transfer can be selected to start from the msb or lsb. figure 14-7 shows the configuration of serial i/o shift register 1 (sio1) and the internal bus. as shown in the figure, msb/lsb can be read/written in reverse form. msb/lsb switching as the start bit can be specified by bit 6 (dir1) of serial operating mode register 1 (csim1). figure 14-7. circuit for switching transfer bit order start bit switching is realized by switching the bit order for data written to sio1. the sio1 shift order remains unchanged. thus, switching between msb-first and lsb-first must be performed before writing data to the shift register. (4) transfer start serial transfer is started by setting transfer data to serial i/o shift register 1 (sio1) when the following two conditions are satisfied. serial interface sio1 operation control bit (bit 7 (csie1) of serial operating mode register 1 (csim1)) = 1 internal serial clock is stopped or sck1 is a high level after 8-bit serial transfer. caution if csie1 is set to 1 after data is written to sio1, transfer does not start. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif1) is set. 7 6 internal bus 1 0 lsb-first msb-first read/write gate si1 shift register 1 (sio1) read/write gate so1 sck1 dq so1 latch 311 chapter 14 serial interface sio1 user s manual u12790ej2v0ud 14.4.3 3-wire serial i/o mode operation with automatic transmit/receive function this 3-wire serial i/o mode is used for transmission/reception of a maximum of 32 bytes of data without the use of software. once transfer is started, the set number of bytes of data prestored in the ram can be transmitted, and the set number of bytes data can be received and stored in the ram. handshake signals (stb and busy) are supported by hardware to transmit/receive data continuously, facilitating connection of an osd (on screen display) lsi and peripheral lsis including an lcd controller/driver. (1) register setting the 3-wire serial i/o mode with automatic transmit/receive function is set using serial operating mode register 1 (csim1), the automatic data transmit/receive control register (adtc), automatic data transmit/receive interval specification register (adti), port mode register 2 (pm2), and port 2 (p2). 312 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (a) serial operating mode register 1 (csim1) csim1 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim1 to 00h. csie1 enable/disable of operation of serial interface sio1 shift register operation serial counter port note 1 0 operation stopped cleared port function 1 operation enabled count operation enabled serial function + port function dir1 start bit 0 msb 1 lsb ate selection of operating mode of serial interface sio1 0 3-wire serial i/o mode 1 3-wire serial i/o mode with automatic transmit/receive function lsck1 chip enable control of sck1 pin 0 sck1 is used as port (p22) when csie1 = 0. sck1 is used for clock output when csie1 = 1. 1 sck1 is fixed to high level when csie1 = 0. sck1 is used for clock output when csie1 = 1. scl11 scl10 selection of serial clock of serial interface sio1 0 0 external clock input to sck1 pin note 2 01f x /2 4 (394 khz) 10f x /2 5 (197 khz) 11f x /2 6 (98.4 khz) notes 1. when csie1 = 0 (sio1 operation stop status), the p20/si1, p21/so1, p22/sck1, p23/stb, and p24/busy pins can be used as port pins. 2. when external clock input is selected by clearing scl11 and scl10 to 0, 0, clear bits 2 (strb) and 1 (busy1) of the automatic data transmit/receive control register (adtc) to 0, 0. <7> csie1 6 dir1 <5> ate 4 lsck1 3 0 2 0 1 scl11 0 scl10 symbol csim1 r/w r/w after reset 00h address ff68h 313 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (b) automatic data transmit/receive control register (adtc) adtc is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets adtc to 00h. <6> <5> <4> <3> <2> <1> <0> <7> symbol adtc re arld erce err trf strb busy1 busy0 ff6ah 00h r/w note 1 address after reset r/w busy1 0 1 1 control of busy input not using busy input note 2 busy input enabled (active high) busy input enabled (active low) busy0 0 1 strb 0 1 control of strobe output strobe output disabled note 3 strobe output enabled trf 1 status of automatic transmit/receive function note 4 end of automatic transmission/reception detected. (this bit is set to 0 upon suspension of automatic transmission/reception or when arld = 0.) automatic transmission/reception in progress. (this bit is set to 1 when data is written to sio1.) r/w r/w r r err 0 1 error detection of automatic transmit/receive function no error (this bit is set to 0 when data is written to sio1) error occurred r/w arld 0 1 operating mode selection of automatic transmit/ receive function single operating mode repetitive operating mode r/w re 0 1 receive control of automatic transmit/receive function receive disabled note 5 receive enabled r/w erce 0 error check control of automatic transmit/ receive function error check disabled error check enabled (only when busy1 = 1) 0 1 314 chapter 14 serial interface sio1 user s manual u12790ej2v0ud notes 1. bits 3 and 4 (trf and err) are read-only bits. 2. when busy1 is reset to 0, p24 (cmos i/o) is used even when bit 7 (csie1) of serial operating mode register 1 (csim1) is set to 1. 3. when strb is reset to 0, p23 (cmos i/o) is used even when bit 7 (csie1) of csim1 is set to 1. 4. when an interrupt is acknowledged, interrupt request flag csiif1 is cleared. therefore, use trf, instead of csiif1, to identify the completion of automatic transmission/reception. 5. when re is reset to 0, p20 (cmos i/o) is used even when bit 7 (csie1) of csim1 is set to 1. caution when an external clock input is selected with bit 1 (csim11) of serial operating mode register 1 (csim1) set to 0, set strb and busy1 of adtc to 0, 0 (when an external clock is input, handshake control cannot be performed). remark : don't care 315 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (c) automatic data transmit/receive interval specification register (adti) this register sets the automatic data transmit/receive function data transfer interval. adti is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets adti to 00h. specification of data transfer interval (f x = 6.3 mhz, f sck = 394 khz) note 2 adti4 adti3 (continued) adti2 adti1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 5.08 s + 0.5/f sck 7.61 s + 0.5/f sck 10.2 s + 0.5/f sck 12.7 s + 0.5/f sck 15.2 s + 0.5/f sck 17.8 s + 0.5/f sck 20.3 s + 0.5/f sck 22.8 s + 0.5/f sck 25.4 s + 0.5/f sck 27.9 s + 0.5/f sck 30.5 s + 0.5/f sck 33.0 s + 0.5/f sck 35.5 s + 0.5/f sck 38.1 s + 0.5/f sck 40.6 s + 0.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti7 0 control of data transfer interval no control of interval by adti note 1 control of interval by adti (adti0 to adti4) 1 adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 316 chapter 14 serial interface sio1 user s manual u12790ej2v0ud notes 1. the interval time is 2/f sck . 2. the data transfer interval time is found from the following expressions (n: value set to adti0 to adti4). <1> n = 0 interval time = 2 + 0.5 f sck f sck <2> n = 1 to 31 interval time = n+1 + 0.5 f sck f sck cautions 1. do not write adti during operation of the automatic data transmit/receive function. 2. be sure to set bits 5 and 6 to 0. 3. when controlling the interval time of automatic transmit/receive data transfer by using adti, busy control is invalid. (refer to 14.4.3 (4) (a) busy control option.) remark f x : system clock oscillation frequency f sck : serial clock frequency specification of data transfer interval (f x = 6.3 mhz, f sck = 394 khz) note 2 adti4 adti3 adti2 adti1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 43.1 s + 0.5/f sck 45.7 s + 0.5/f sck 48.2 s + 0.5/f sck 50.8 s + 0.5/f sck 53.3 s + 0.5/f sck 55.8 s + 0.5/f sck 58.4 s + 0.5/f sck 60.9 s + 0.5/f sck 63.5 s + 0.5/f sck 66.0 s + 0.5/f sck 68.5 s + 0.5/f sck 71.1 s + 0.5/f sck 73.6 s + 0.5/f sck 76.1 s + 0.5/f sck 78.6 s + 0.5/f sck 81.2 s + 0.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 317 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (d) port mode register 2 (pm2) pm2 is a register that sets input/output of port 2 in 1-bit units. when using the p21/so1 pin as a serial data output, set pm21 and the output latch of p21 to 0. when using the p22/sck1 pin as a clock output, set pm22 and the output latch of p22 to 0. when using the p25/stb pin as a strobe output, set pm25 and the output latch of p25 to 0. when using the p20/si1 pin as a serial data input, the p22/sck1 pin as a clock input, and the p24/busy pin as a busy input, set pm20, pm22, and pm24 to 1. at this time, the output latches of p20, p22, and p24 can be either 0 or 1. pm2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets the value of pm2 to ffh. address: ff22h after reset: ffh r/w symbol 76543210 pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2n i/o mode selection of p2n pin (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 318 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (2) automatic transmit/receive data setting (a) transmit data setting <1> write transmit data from the least significant address fac0h of buffer ram (up to fadfh). the transmit data should be in the order of higher address to lower address. <2> set the value obtained by subtracting 1 from the number of transmit data bytes to the automatic data transmit/receive address pointer (adtp). (b) automatic transmit/receive mode setting <1> set bit 7 (csie1) and bit 5 (ate) of serial operating mode register 1 (csim1) to 1. <2> set bit 7 (re) of the automatic data transmit/receive control register (adtc) to 1. <3> set the data transmit/receive interval in the automatic data transmit/receive interval specification register (adti). <4> write any value to serial i/o shift register 1 (sio1) (transfer start trigger). caution writing any value to sio1 orders the start of automatic transmit/receive operation; the written value has no meaning. the following operations are automatically carried out when (a) and (b) are carried out. after the buffer ram data specified by adtp is transferred to sio1, transmission is carried out (start of automatic transmission/reception). the received data is written to the buffer ram address specified by adtp. adtp is decremented and the next data transmission/reception is carried out. data transmission/ reception continues until the adtp decremental output becomes 00h and address fac0h data is output (end of automatic transmission/reception). when automatic transmission/reception is terminated, bit 3 (trf) of adtc is cleared to 0. 319 chapter 14 serial interface sio1 user? manual u12790ej2v0ud (3) communication operation (a) basic transmit/receive mode this transmit/receive mode is the same as the 3-wire serial i/o mode in which the specified number of data are transmitted/received in 8-bit units. serial transfer is started when any data is written to serial i/o shift register 1 (sio1) while bit 7 (csie1) of serial operating mode register 1 (csim1) is set to 1. upon completion of transmission of the last byte, the interrupt request flag (csiif1) is set. the termination of automatic transmission/reception should be checked by using bit 3 (trf) of the automatic data transmit/ receive control register (adtc), not by csiif1 because the csiif1 interrupt request flag is cleared if an interrupt is acknowledged. if busy control and strobe control are not executed, the p23/stb and p24/busy pins can be used as normal i/o ports. figure 14-8 shows the basic transmit/receive mode operation timing, and figure 14-9 shows the operation flowchart. figure 14-10 shows the buffer ram operation in 6-byte transmission. figure 14-8. basic transmit/receive mode operation timing cautions 1. because, in the basic transmit/receive mode, the automatic transmit/receive function writes/reads data to/from the buffer ram after 1-byte transmission/reception, an interval is inserted until the next transmission/reception. as the buffer ram write/ read is performed at the same time as cpu processing, the maximum interval is dependent upon the cpu processing and the value of the automatic data transmit/ receive interval specification register (adti) (refer to (6) automatic data transmit/ receive interval). 2. when trf is cleared, the so1 pin becomes low level. remark csiif: interrupt request flag trf: bit 3 of the automatic data transmit/receive control register (adtc) sck1 so1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 csiif1 trf si1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval 320 chapter 14 serial interface sio1 user s manual u12790ej2v0ud figure 14-9. basic transmit/receive mode flowchart adtp: automatic data transmit/receive address pointer adti: automatic data transmit/receive interval specification register sio1: serial i/o shift register 1 trf: bit 3 of the automatic data transmit/receive control register (adtc) start write transmit data in buffer ram set adtp to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmit/receive operation interval time to adti write any data to sio1 (start trigger) write transmit data from buffer ram to sio1 transmission/reception operation write receive data from sio1 to buffer ram pointer value = 0 no trf = 0 no end yes yes decrement pointer value software execution hardware execution software execution 321 chapter 14 serial interface sio1 user s manual u12790ej2v0ud in 6-byte transmission/reception (bit 6 (arld) and bit 7 (re) of the automatic data transmit/receive control register (adtc) = 0 and 1, respectively) in basic transmit/receive mode, the buffer ram operates as follows. (i) before transmission/reception (refer to figure 14-10 (a)) after any data has been written to sio1 (start trigger: this data is not transferred), transmit data 1 (t1) is transferred from the buffer ram to sio1. when transmission of the first byte is completed, receive data 1 (r1) is transferred from sio1 to the buffer ram, and the automatic data transmit/ receive address pointer (adtp) is decremented. then transmit data 2 (t2) is transferred from the buffer ram to sio1. (ii) 4th byte transmit/receive point (refer to figure 14-10 (b)) transmission/reception of the third byte is completed, and transmit data 4 (t4) is transferred from the buffer ram to sio1. when transmission of the fourth byte is completed, receive data 4 (r4) is transferred from sio1 to the buffer ram, and adtp is decremented. (iii) completion of transmission/reception (refer to figure 14-10 (c)) when transmission of the sixth byte is completed, receive data 6 (r6) is transferred from sio1 to the buffer ram, and the interrupt request flag (csiif1) is set (intcsi1 generation). figure 14-10. buffer ram operation in 6-byte transmission/reception (in basic transmit/receive mode) (1/2) (a) before transmission/reception transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h receive data 1 (r1) sio1 0 csiif1 5 adtp _ 1 322 chapter 14 serial interface sio1 user s manual u12790ej2v0ud figure 14-10. buffer ram operation in 6-byte transmission/reception (in basic transmit/receive mode) (2/2) (b) 4th byte transmission/reception (c) completion of transmission/reception receive data 1 (r1) receive data 2 (r2) receive data 3 (r3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h receive data 4 (r4) sio1 0 csiif1 2 adtp _ 1 receive data 1 (r1) receive data 2 (r2) receive data 3 (r3) receive data 4 (r4) receive data 5 (r5) receive data 6 (r6) fadfh fac5h fac0h sio1 1 csiif1 0 adtp 323 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (b) basic transmit mode in this mode, the specified number of 8-bit unit data are transmitted. serial transfer is started when any data is written to serial i/o shift register 1 (sio1) while bit 7 (csie1) of serial operating mode register 1 (csim1) is set to 1, and bit 7 (re) of the automatic data transmit/receive control register (adtc) is set to 0. upon completion of transmission of the last byte, the interrupt request flag (csiif1) is set. the termination of automatic transmission/reception should be checked by using bit 3 (trf) of the automatic data transmit/ receive control register (adtc), not by csiif1. if a receive operation, busy control, and strobe control are not executed, the p20/si1, p23/stb and p24/ busy pins can be used as normal i/o pins. figure 14-11 shows the basic transmit mode operation timing, and figure 14-12 shows the operation flowchart. figure 14-13 shows the buffer ram operation when repeatedly transmitting 6 bytes. figure 14-11. basic transmit mode operation timing cautions 1. because, in the basic transmit mode, the automatic transmit/receive function reads data from the buffer ram after 1-byte transmission, an interval is inserted until the next transmission. as the buffer ram read is performed at the same time as cpu processing, the maximum interval is dependent upon the cpu processing and the value of the automatic data transmit/receive interval specification register (adti) (refer to (6) automatic data transmit/receive interval). 2. when trf is cleared, the so1 pin becomes low level. remark csiif: interrupt request flag trf: bit 3 of the automatic data transmit/receive control register (adtc) sck1 so1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 csiif1 trf interval 324 chapter 14 serial interface sio1 user s manual u12790ej2v0ud figure 14-12. basic transmit mode flowchart adtp: automatic data transmit/receive address pointer adti: automatic data transmit/receive interval specification register sio1: serial i/o shift register 1 trf: bit 3 of the automatic data transmit/receive control register (adtc) start write transmit data in buffer ram set adtp to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmit/receive operation interval time to adti write any data to sio1 (start trigger) write transmit data from buffer ram to sio1 transmission operation pointer value = 0 no trf = 0 no end yes yes decrement pointer value software execution hardware execution software execution 325 chapter 14 serial interface sio1 user s manual u12790ej2v0ud in 6-byte transmission (bit 6 (arld) and bit 7 (re) of the automatic data transmit/receive control register (adtc) are 0) in basic transmit mode, the buffer ram operates as follows. (i) before transmission (refer to figure 14-13 (a)) after any data has been written to sio1 (start trigger: this data is not transferred), transmit data 1 (t1) is transferred from the buffer ram to sio1. when transmission of the first byte is completed, adtp is decremented. then transmit data 2 (t2) is transferred from the buffer ram to sio1. (ii) 4th byte transmission point (refer to figure 14-13 (b)) transmission of the third byte is completed, and transmit data 4 (t4) is transferred from the buffer ram to sio1. when transmission of the fourth byte is completed, adtp is decremented. (iii) completion of transmission/reception (refer to figure 14-13 (c)) when transmission of the sixth byte is completed, the interrupt request flag (csiif1) is set (intcsi1 generation). figure 14-13. buffer ram operation in 6-byte transmission (in basic transmit mode) (1/2) (a) before transmission transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 0 csiif1 5 adtp _ 1 326 chapter 14 serial interface sio1 user s manual u12790ej2v0ud figure 14-13. buffer ram operation in 6-byte transmission (in basic transmit mode) (2/2) (b) 4th byte transmission point (c) completion of transmission/reception transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 0 csiif1 2 adtp _ 1 transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 1 csiif1 0 adtp 327 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (c) repeat transmit mode in this mode, data stored in the buffer ram is transmitted repeatedly. serial transfer is started by writing any data to serial i/o shift register 1 (sio1) when bit 7 (csie1) of serial operating mode register 1 (csim1) is set to 1, and bit 7 (re) of the automatic data transmit/receive control register (adtc) is set to 0. unlike the basic transmit mode, after the last byte (data in address fac0h) has been transmitted, the interrupt request flag (csiif1) is not set, the value when the transmission was started is set in the automatic data transmit/receive address pointer (adtp) again, and the buffer ram contents are transmitted again. when a reception operation, busy control, and strobe control are not performed, the p20/si1, p23/stb and p24/busy pins can be used as ordinary i/o pins. the repeat transmit mode operation timing is shown in figure 14-14, and the operation flowchart in figure 14-15. figure 14-14. repeat transmit mode operation timing caution since, in the repeat transmit mode, a read is performed on the buffer ram after the transmission of one byte, the interval is included in the period up to the next transmission. as the buffer ram read is performed at the same time as cpu processing, the maximum interval is dependent upon the cpu processing and the value of the automatic data transmit/receive interval specification register (adti) (refer to (6) automatic data transmit/ receive interval). d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval interval d7 d6 d5 sck1 so1 328 chapter 14 serial interface sio1 user s manual u12790ej2v0ud figure 14-15. repeat transmit mode flowchart adtp: automatic data transmit/receive address pointer adti: automatic data transmit/receive interval specification register sio1: serial i/o shift register 1 start write transmit data in buffer ram set adtp to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmit/receive operation interval time to adti write any data to sio1 (start trigger) write transmit data from buffer ram to sio1 transmission operation pointer value = 0 no yes decrement pointer value software execution hardware execution reset adtp 329 chapter 14 serial interface sio1 user s manual u12790ej2v0ud in 6-byte transmission (bit 6 (arld) and bit 7 (re) of the automatic data transmit/receive control register (adtc) are 1 and 0, respectively) in repeat transmit mode, the buffer ram operates as follows. (i) before transmission (refer to figure 14-16 (a)) after any data has been written to sio1 (start trigger: this data is not transferred), transmit data 1 (t1) is transferred from the buffer ram to sio1. when transmission of the first byte is completed, adtp is decremented. then transmit data 2 (t2) is transferred from the buffer ram to sio1. (ii) upon completion of transmission of 6 bytes (refer to figure 14-16 (b)) when transmission of the sixth byte is completed, the interrupt request flag (csiif1) is not set. the previous pointer value is assigned to adtp. (iii) 7th byte transmission point (refer to figure 14-16 (c)) transmit data 1 (t1) is transferred from the buffer ram to sio1 again. when transmission of the first byte is completed, adtp is decremented. then transmit data 2 (t2) is transferred from the buffer ram to sio1. figure 14-16. buffer ram operation in 6-byte transmission (in repeat transmit mode) (1/2) (a) before transmission transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 0 csiif1 5 adtp _ 1 330 chapter 14 serial interface sio1 user s manual u12790ej2v0ud figure 14-16. buffer ram operation in 6-byte transmission (in repeat transmit mode) (2/2) (b) upon completion of transmission of 6 bytes (c) 7th byte transmission point transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 0 csiif1 0 adtp transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 0 csiif1 5 adtp _ 1 331 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (d) automatic transmission/reception suspension and restart automatic transmission/reception can be temporarily suspended by setting bit 7 (csie1) of serial operating mode register 1 (csim1) to 0. if 8-bit data transfer is in progress, the transmission/reception is not suspended if bit 7 (csie1) is set to 0. it is suspended upon completion of 8-bit data transfer. when suspended, bit 3 (trf) of the automatic data transmit/receive control register (adtc) is set to 0 after transfer of the 8th bit, and all the port pins that function alternately as serial interface pins (p20/si1, p21/so1, p22/sck1, p23/stb and p24/busy) are set to the port mode. during restart of transmission/reception, the remaining data can be transferred by setting csie1 to 1 and writing any data to serial i/o shift register 1 (sio1). cautions 1. if the halt instruction is executed during automatic transmission/reception, transfer is suspended and the halt mode is set if 8-bit data transfer is in progress. 2. when suspending automatic transmission/reception, do not change the operating mode to 3-wire serial i/o mode while trf = 1. figure 14-17. automatic transmission/reception suspension and restart csie1: bit 7 of serial operating mode register 1 (csim1) sck1 so1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 si1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 csie1 = 0 (suspend command) suspend restart command csie1 = 1, write to sio1 332 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (4) synchronization control busy control and strobe control are functions used to synchronize transmission/reception between the master device and a slave device. by using these functions, a shift in bits being transmitted or received can be detected. (a) busy control option busy control is a function used to keep the serial transmission/reception by the master device waiting while the busy signal output by a slave device to the master is active. when using this busy control option, the following conditions must be satisfied. bit 5 (ate) of serial operating mode register 1 (csim1) is set to 1. bit 1 (busy1) of the automatic data transmit/receive control register (adtc) is set to 1. figure 14-18 shows the system configuration of the master device and a slave device when the busy control option is used. figure 14-18. system configuration when busy control option is used the master device inputs the busy signal output by the slave device to the busy/p24 pin. the master device samples the input busy signal in synchronization with the falling of the serial clock. even if the busy signal becomes active while 8-bit data is being transmitted or received, transmission/reception by the master is not kept waiting. if the busy signal is active at the rising edge of the serial clock 2 clocks after completion of transmission/reception of the 8-bit data, the busy input becomes valid. after that, the master transmission/reception is kept waiting while the busy signal is active. the active level of the busy signal is set by bit 0 (busy0) of adtc. busy0 = 0: active high busy1 = 1: active low sck1 so1 si1 sck1 so1 si1 busy master device ( pd178078, 178098a subseries) slave device 333 chapter 14 serial interface sio1 user s manual u12790ej2v0ud when using the busy control option, select the internal clock as the serial clock. control by the busy signal cannot be implemented with the external clock. figure 14-19 shows the operation timing when the busy control option is used. caution busy control cannot be used simultaneously with the interval time control function of the automatic data transmit/receive interval specification register (adti). if used, busy control is invalid. figure 14-19. operation timing when busy control option is used (when busy0 = 0) caution if trf is cleared, the so1 pin goes low. remark csiif1: interrupt request flag trf: bit 3 of the automatic data transmit/receive control register (adtc) when the busy signal becomes inactive, waiting is released. if the sampled busy signal is inactive, transmission/reception of the next 8-bit data is started at the falling edge of the next clock. because the busy signal is asynchronous to the serial clocks, it takes up to 1 clock until the busy signal, even if made inactive by the slave, is sampled. it takes 0.5 clocks until data transfer is started after the busy signal was sampled. to accurately release waiting, the slave must keep the busy signal inactive for at least the duration of 1.5 clocks. figure 14-20 shows the timing of the busy signal and wait release. this figure shows an example where the busy signal is active as soon as transmission/reception has been started. sck1 d7 so1 si1 csiif1 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy trf busy input released busy input valid wait 334 chapter 14 serial interface sio1 user s manual u12790ej2v0ud figure 14-20. busy signal and wait release (when busy0 = 0) (b) strobe control option strobe control is a function used to synchronize data transmission/reception between the master and a slave device. the master device outputs the strobe signal from the stb/p23 pin when 8-bit transmission/ reception has been completed. by this signal, the slave device can determine the timing of the end of data transmission. therefore, synchronization is established even if a bit shift occurs due to noise on the serial clock, and transmission of the next byte is not affected by the bit shift. to use the strobe control option, the following conditions must be satisfied. bit 5 (ate) of serial operating mode register 1 (csim1) is set to 1. bit 2 (strb) of the automatic data transmit/receive control register (adtc) is set to 1. a strobe signal is output from the stb/p23 pin for the duration of 1 clock in synchronization with the falling of the ninth serial clock. figure 14-21 shows the operation timing when the strobe control option is used. figure 14-21. operation timing when strobe control option is used d7 d6 d5 d4 d3 d2 d1 d0 d0 d7 d6 d5 d4 d3 d2 d1 d7 d6 d5 d4 d3 d2 d1 d0 d0 d7 d6 d5 d4 d3 d2 d1 strobe signal output strobe signal output sck1 so1 si1 stb csiif1 sck1 d7 so1 si1 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy (active high) 1.5 clocks (min.) busy input released busy input valid wait if made inactive immediately after sampled 335 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (c) busy & strobe control option usually, the busy control and strobe control options are simultaneously used as handshake signals. in this case, the strobe signal is output from the stb/p23 pin, and the busy/p24 pin is sampled, and transmission/reception can be kept waiting while the busy signal is input. when the strobe control option is not used, the p23/stb pin can be used as a normal i/o port pin. to use the busy & strobe control option, the following conditions must be satisfied. bit 5 (ate) of serial operating mode register 1 (csim1) is set to 1. bit 2 (strb) and bit 1 (busy1) of the automatic data transmit/receive control register (adtc) are set to 1. the active level of the busy signal is set by bit 0 (busy0) of adtc. busy0 = 0: active high busy1 = 1: active low figure 14-22 shows the operation timing when the busy & strobe control option is used. when the strobe control option is used, the interrupt request flag (csiif1) that is set on completion of transmission/reception is set after the strobe signal is output. 336 chapter 14 serial interface sio1 user s manual u12790ej2v0ud figure 14-22. operation timing when busy & strobe control option is used (when busy0 = 0) caution when trf is cleared, the so1 pin goes low. remark csiif1: interrupt request flag trf: bit 3 of the automatic data transmit/receive control register (adtc) stb sck1 d7 so1 si1 csiif1 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy trf busy input released busy input valid 337 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (d) bit shift detection by busy signal during automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock signal output by the master device. unless the strobe control option is used at this time, the bit shift affects transmission of the next byte. in this case, the master can detect the bit shift by checking the busy signal during transmission by using the busy control option. a bit shift is detected by using the busy signal as follows. the slave outputs the busy signal after the rising of the eighth serial clock during data transmission/ reception (to not keep transmission/reception waiting by the busy signal at this time, make the busy signal inactive within 2 clocks). the master samples the busy signal in synchronization with the falling of the leading side of the serial clock. if a bit shift has not occurred, all the eight serial clocks that have been sampled are inactive. if the sampled serial clocks are active, it is assumed that a bit shift has occurred, and error processing is executed (by setting bit 4 (err) of the automatic transmit/receive control register (adtc) to 1). figure 14-23 shows the operation timing of the bit shift detection function by the busy signal. figure 14-23. operation timing of bit shift detection function by busy signal (when busy0 = 1) csiif1: interrupt request flag csie1: bit 7 of serial operating mode register 1 (csim1) err: bit 4 of the automatic data transmit/receive control register (adtc) sck1 (slave) d7 so1 si1 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy csiif1 csie1 err d7 d7 busy not detected error interrupt request generated error detected bit shift due to noise sck1 (master) 338 chapter 14 serial interface sio1 user s manual u12790ej2v0ud (5) timing of interrupt request signal generation the interrupt signal is generated in synchronization with the timing shown in table 14-2. table 14-2. timing of interrupt request signal generation operating mode timing of interrupt request signal single mode master mode 10th serial clock at end of transfer slave mode 8th serial clock at end of transfer repeat transmit mode not generated if bit shift occurs during transmission/reception 8th serial clock (6) interval time of automatic transmission/reception because read/write to/from the buffer ram using the automatic transmit/receive function is performed asynchronously to the cpu processing, the interval time is dependent on the cpu processing at the timing of the eighth rising of the serial clock and the set value of the automatic data transmit/receive interval specification register (adti). whether the interval time is dependent on adti is selected by setting bit 7 (adti7) of adti. if adti7 is reset to 0, the interval time is 2/f sck . if adti7 is set to 1, the interval time determined by the set contents of adti or the interval time by the cpu processing is selected, whichever is greater. figure 14-24 shows the interval time of automatic transmission/reception. remark f sck : serial clock frequency figure 14-24. interval time of automatic transmission/reception the following expression must be satisfied to access the buffer ram. 1 transfer cycle read access + write access + cpu buffer ram access in the case of a high-speed cpu & low-speed sck note , the interval time is not necessary. in the case of a low-speed cpu & high-speed sck note , the interval time is necessary. in this case, make sure that a sufficient interval time elapses, by using the automatic data transmit/receive interval specification register (adti), so that the above expression is satisfied. note the speeds of the cpu clock and sck differ depending on the type of cpu core. interval sck1 d7 so1 si1 csiif1 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 339 user? manual u12790ej2v0ud chapter 15 serial interface sio3 15.1 function of serial interface sio3 serial interface sio3 has the following two modes. (1) operation stop mode this mode is used when serial transfer is not performed. for details, refer to 15.4.1 . (2) 3-wire serial i/o mode (msb-first) in this mode, 8-bit data is transferred by using three lines: a serial clock (sck3), serial output (so3), and serial input (si3). because transmission and reception can be executed simultaneously in this mode, the processing time of data transfer can be shortened. the first bit of the 8-bit data to be transferred is the msb. the 3-wire serial i/o mode is useful for connecting a peripheral i/o or display controller with a clocked serial interface. for details, refer to 15.4.2 . figure 15-1 shows the block diagram of serial interface sio3. figure 15-1. block diagram of serial interface sio3 internal bus 8 8 direction controller interrupt request signal generator selector serial clock counter serial clock controller serial i/o shift register 3 (sio3) si3/p70 so3/p71 p71 output latch pm71 pm72 sck3/p72 intcsi3 f x /2 4 f x /2 5 f x /2 6 p72 output latch 340 chapter 15 serial interface sio3 user? manual u12790ej2v0ud 15.2 configuration of serial interface sio3 the serial interface sio3 consists of the following hardware. table 15-1. configuration of serial interface sio3 item configuration register serial i/o shift register 3 (sio3) control registers serial operating mode register 3 (csim3) port mode register (pm7) port 7 (p7) (1) serial i/o shift register 3 (sio3) this 8-bit register converts parallel data into serial data and transmits or receives serial data (shift operation) in synchronization with the serial clock. sio3 is set by an 8-bit memory manipulation instruction. a serial operation is started by writing or reading data to or from sio3 when bit 7 (csie3) of serial operating mode register 3 (csim3) is 1. data written to sio3 is output to a serial output line (so3) for transmission. data is read to sio3 from a serial input line (si3) for reception. the value of this register is undefined after reset. caution do not execute an access to sio3 during transfer other than a transfer start trigger access (read operations are disabled when mode0 = 0, and write operations are disabled when mode0 = 1). 341 chapter 15 serial interface sio3 user? manual u12790ej2v0ud 15.3 registers controlling serial interface sio3 the following three registers control serial interface sio3. serial operating mode register 3 (csim3) port mode register 7 (pm7) port 7 (p7) (1) serial operating mode register 3 (csim3) this register selects the serial clock of sio3 and the operating mode, and enables or disables the operation. csim3 is set by a 1-bit or 8-bit memory manipulation instruction. the value of this register is initialized to 00h after reset. figure 15-2. format of serial operating mode register 3 (csim3) csie3 enable/disable of sio3 operation shift register operation serial counter port 0 operation disabled cleared port function note 1 1 operation enabled counter operation enabled serial function + port function note 2 mode transfer operating mode flag operating mode transfer start trigger so3 output 0 transmit or transmit/receive mode sio3 write serial output 1 receive only mode sio3 read fixed to low level note 3 scl31 scl30 selection of clock 0 0 external clock input to sck3 01f x /2 4 (394 khz) 10f x /2 5 (197 khz) 11f x /2 6 (98.4 khz) notes 1. the si3, so3, and sck3 pins can be used as port pins when csie3 = 0 (when sio3 operation is stopped). 2. when csie3 = 1 (when sio3 operation is enabled), the si3 pin can be used as a port pin if only the transmission function is used, and the so3 pin can be used as a port pin in the receive mode. 3. this pin can be used as a port pin (p71). remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 6.3 mhz <7>6543 csie3 0000 2 mode 1 scl31 0 scl30 symbol csim3 r/w r/w after reset 00h address ff6fh 342 chapter 15 serial interface sio3 user? manual u12790ej2v0ud (2) port mode register 7 (pm7) pm7 is a register that sets input/output of port 7 in 1-bit units. when using the p71/so3 pin as a serial data output, set pm71 and the output latch of p71 to 0. when using the p72/sck3 pin as a clock output, set pm72 and the output latch of p72 to 0. when using the p70/si3 pin as a serial data input and the p72/sck3 pin as a clock input, set pm70 and pm72 to 1. at this time, the output latches of p70 and p72 can be either 0 or 1. pm7 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets the value of pm7 to ffh. figure 15-3. format of port mode register 7 (pm7) address: ff27h after reset: ffh r/w symbol 76543210 pm7 pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 pm7n i/o mode selection of p7n pin (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 343 chapter 15 serial interface sio3 user? manual u12790ej2v0ud 15.4 operation of serial interface sio3 this section explains the two modes of serial interface sio3. 15.4.1 operation stop mode in this mode, serial transfer is not performed. the p70/si3, p71/so3, and p72/sck3 pins can be used as ordinary i/o port pins. (1) register setting the operation stop mode is set by using serial operating mode register 3 (csim3). csim3 is set by a 1-bit or 8-bit memory manipulation instruction. the value of this register is initialized to 00h after reset. csie3 enable/disable of sio3 operation shift register operation serial counter port 0 operation disabled cleared port function note 1 1 operation enabled count operation enabled serial function + port function note 2 notes 1. the si3, so3, and sck3 pins can be used as port pins when csie3 = 0 (when sio3 operation is stopped). 2. when csie3 = 1 (when sio3 operation is enabled), the si3 pin can be used as a port pin if only the transmission function is used, and the so3 pin can be used as a port pin in the receive mode. r/w r/w address ff6fh after reset 00h symbol csim3 <7> csie3 6 0 5 0 4 0 3 0 2 mode 1 scl31 0 scl30 344 chapter 15 serial interface sio3 user s manual u12790ej2v0ud 15.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connecting a peripheral i/o or display controller equipped with a clocked serial interface. in this mode, communication is executed by using three lines: a serial clock (sck3), serial output (so3), and serial input (si3). (1) register setting the 3-wire serial i/o mode is set by using serial operating mode register 3 (csim3). (a) serial operation mode register 3 (csim3) this register is set by a 1-bit or 8-bit memory manipulation instruction. the value of this register is initialized to 00h after reset. csie3 enable/disable of sio3 operation shift register operation serial counter port 0 operation disabled cleared port function note 1 1 operation enabled counter operatio enabled serial function + port function note 2 mode transfer operation mode flag operating mode transfer start trigger so3 output 0 transmit or transmit/receive mode sio3 write serial output 1 receive-only mode sio3 read fixed to low level note 3 scl31 scl30 selection of clock 0 0 external clock input to sck3 01f x /2 4 (394 khz) 10f x /2 5 (197 khz) 11f x /2 6 (98.4 khz) notes 1. the si3, so3, and sck3 pins can be used as port pins when csie3 = 0 (when sio3 operation is stopped). 2. when csie3 = 1 (when sio3 operation is enabled), the si3 pin can be used as a port pin if only the transmission function is used, and the so3 pin can be used as a port pin in the receive mode. 3. this pin can be used as a port pin (p71). remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 6.3 mhz symbol csim3 <7> csie3 6 0 5 0 4 0 3 0 2 mode 1 scl31 0 scl30 r/w r/w after reset 00h address ff6fh 345 chapter 15 serial interface sio3 user s manual u12790ej2v0ud (b) port mode register 7 (pm7) pm7 is a register that sets input/output of port 7 in 1-bit units. when using the p71/so3 pin as a serial data output, set pm71 and the output latch of p71 to 0. when using the p72/sck3 pin as a clock output, set pm72 and the output latch of p72 to 0. when using the p70/si3 pin as a serial data input and the p72/sck3 pin as a clock input, set pm70 and pm72 to 1. at this time, the output latches of p70 and p72 can be either 0 or 1. pm7 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets the value of pm7 to ffh. address: ff27h after reset: ffh r/w symbol 76543210 pm7 pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 pm7n i/o mode selection of p7n pin (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 346 chapter 15 serial interface sio3 user s manual u12790ej2v0ud sck3 si3 so3 csiif3 transfer starts at fallin g ed g e of sck3 transfer ends 12345678 di7 di6 di5 do7 do6 do5 di4 di3 di2 do4 do3 do2 di1 di0 do1 do0 (2) communication operation in the 3-wire serial i/o mode, data is transmitted or received in 8-bit units. data is transmitted or received in synchronization with the serial clock. the shift operation of serial i/o shift register 3 (sio3) is performed at the falling edge of the serial clock (sck3). the transmit data is held in so3 and is output from the so3 pin. the receive data input to the si3 pin is latched to sio3 at the falling edge of the serial clock. when 8-bit data has been transferred, the operation of sio3 is automatically stopped, and the interrupt request flag (csiif3) is set. figure 15-4. timing in 3-wire serial i/o mode (3) starting transfer serial transfer is started by writing (or reading) transfer data to serial i/o shift register 3 (sio3) when the following conditions are satisfied. operation control bit of sio3 (bit 7 (csie3) of serial operation mode register 3 (csim3)) = 1 if the internal serial clock is stopped or sck3 is high after transfer of 8-bit serial data transmit/receive mode transfer is started if sio3 is written when bit 7 (csie3) of csim3 = 1, and bit 2 (mode) = 0 receive mode transfer is started if sio3 is read when bit 7 (csie3) of csim3 = 1, and bit 2 (mode) = 1 caution serial transfer is not started even if 1 is written to csie3 after data is written to sio3. on completion of transfer of the 8-bit data, serial transfer is automatically stopped, and the interrupt request flag (csiif3) is set. 347 user? manual u12790ej2v0ud chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) 16.1 functions of serial interface uart0 serial interface uart0 has the following two modes. (1) operation stop mode in this mode, serial transfer is not performed. for details, refer to 16.4.1 . (2) asynchronous serial interface (uart) mode this mode is used to transmit or receive 1-byte data following a start bit. full duplex operation can be executed in this mode. because a uart-dedicated baud rate generator is provided, communication can be executed at a wide range of baud rates. moreover, midi standard baud rate (31.25 kbps) can also be generated by using the uart-dedicated baud rate generator. for details, refer to 16.4.2 . figure 16-1 shows the block diagram of serial interface uart0. figure 16-1. block diagram of serial interface uart0 note for the configuration of the baud rate generator, refer to figure 16-2. rxd0/p74 txd0/p75 pe0 fe0 ove0 intser0 intst0 pm75 f x /2 to f x /2 8 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 0 intsr0 internal bus asynchronous serial interface mode register 0 (asim0) asynchronous serial interface status register 0 (asis0) receive buffer register 0 (rxb0) receive shift register 0 (rx0) transmit shift register (txs0) transmission controller (parity added) reception controller (parity check) output latch (p75) baud rate generator note 348 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud figure 16-2. block diagram of baud rate generator remark txed: bit 7 of asynchronous serial interface mode register 0 (asim0) rxed: bit 6 of asynchronous serial interface mode register 0 (asim0) tps0 1 tps02 tps00 f x /2 to f x /2 8 34 mdl0 3 mdl0 2 mdl0 1 mdl00 txe0 match match transmission clock selector reception clock rxe0 start bit detection 1/2 5-bit counter internal bus baud rate generator control register 0 (brgc0) encoder 5-bit counter 1/2 349 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud 16.2 configuration of serial interface uart0 serial interface uart0 consists of the following hardware. table 16-1. configuration of serial interface uart0 item configuration registers transmit shift register 0 (txs0) receive shift register 0 (rx0) receive buffer register 0 (rxb0) control registers asynchronous serial interface mode register 0 (asim0) asynchronous serial interface status register 0 (asis0) baud rate generator control register 0 (brgc0) port mode register 7 (pm7) port 7 (p7) (1) transmit shift register 0 (txs0) this register stores transmit data. the data written to txs0 is transmitted as serial data. when the data length is specified to be 7 bits, bits 0 to 6 of the data written to txs0 are transferred as transmit data. the transmission operation is started by writing data to txs0. txs0 is written by an 8-bit memory manipulation instruction, but it cannot be read. the value of this register is set to ffh after reset. caution do not write data to txs0 during transmission. because txs0 and receive buffer register 0 (rxb0) are assigned to the same address, if this address is read, the value of rxb0 is read. (2) receive shift register 0 (rx0) this register converts the serial data input to the rxd0 pin into parallel data. when 1 byte of data has been received, the receive data is transferred to receive buffer register 0 (rxb0). rxb0 cannot be directly manipulated by software. (3) receive buffer register 0 (rxb0) this register holds receive data. each time 1 byte of data has been received, new receive data is transferred from receive shift register 0 (rx0). if the data length is specified to be 7 bits, the receive data is transferred to bits 0 to 6 of rxb0, and the msb of rxb0 is always 0. rxb0 can be read by an 8-bit memory manipulation instruction, but it cannot be written. the value of this register is set to ffh after reset. caution because rxb0 and transmit shift register 0 (txs0) are assigned to the same address, if data is written to this address, the value is written to txs0. 350 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud (4) transmission controller this circuit controls the transmission operation by appending a start bit, parity bit, and stop bit to the data written to transmit shift register 0 (txs0) according to the contents of asynchronous serial interface mode register 0 (asim0). (5) reception controller this circuit controls the reception operation according to the contents of asynchronous serial interface mode register 0 (asim0). it also checks for errors such as a parity error during reception and, if an error is detected, writes a value identifying the error to asynchronous serial interface status register 0 (asis0). 351 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user? manual u12790ej2v0ud 16.3 registers controlling serial interface uart0 the following five registers control serial interface uart0. asynchronous serial interface mode register 0 (asim0) asynchronous serial interface status register 0 (asis0) baud rate generator control register 0 (brgc0) port mode register 7 (pm7) port 7 (p7) (1) asynchronous serial interface mode register 0 (asim0) this 8-bit register controls the serial transfer operation of serial interface uart0. asim0 is set by a 1-bit or 8-bit memory manipulation instruction. the value of this register is initialized to 00h after reset. figure 16-3 shows the format of asim0. 352 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user? manual u12790ej2v0ud figure 16-3. format of asynchronous serial interface mode register 0 (asim0) txe0 rxe0 operating mode function of rxd0/p74 pin function of txd0/p75 pin 0 0 operation stop port function (p74) port function (p75) 0 1 uart mode (reception only) serial function (rxd0) 1 0 uart mode (transmission only) port function (p74) serial function (txd0) 1 1 uart mode serial function (rxd0) (transmission/reception) ps01 ps00 specification of parity bit 0 0 no parity 0 1 0 parity always appended during transmission. parity not checked during reception (parity error does not occur). 1 0 odd parity 1 1 even parity cl0 specification of character length 0 7 bits 1 8 bits sl0 specification of stop bit length of transmit data 0 1 bit 1 2 bits isrm0 control of reception completion interrupt in case of error 0 reception completion interrupt request generated in case of error 1 reception completion interrupt request not generated in case of error note be sure to reset bit 0 of asim0 to 0. cautions 1. before changing the operation mode, stop the serial transmission/reception operation. 2. set port mode register 7 (pm7) and the output latch of port 7 (p7) as follows in the uart mode. reset the output latch to 0. during reception set the p74/rxd0 pin to the input mode (pm74 = 1). during transmission set the p75/txd0 pin to the output mode (pm75 = 0, p75 = 0). during transmission/reception set p74 to the input mode and p75 to the output mode. r/w r/w address ff5ah after reset 00h symbol asim0 <7> txe0 <6> rxe0 5 ps01 4 ps00 3 cl0 2 sl0 1 isrm0 0 0 note 353 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud (2) asynchronous serial interface status register 0 (asis0) this register indicates the type of error when a reception error occurs in the uart mode. asis0 is set by an 8-bit memory manipulation instruction. the value of this register is initialized to 00h after reset. figure 16-4. format of asynchronous serial interface register 0 (asis0) pe0 parity error flag 0 no parity error 1 parity error occurred (if parity of transmit data did not match). fe0 framing error flag 0 no framing error 1 framing error occurred note 1 (if stop bit was not detected). ove0 overrun error flag 0 no overrun error 1 overrun error occurred note 2 (if next reception operation was completed before data was read from receive buffer register 0). notes 1. even when the stop bit length is set to 2 bits by bit 2 (sl0) of asynchronous serial interface mode register 0 (asim0), only 1 stop bit is detected during reception. 2. be sure to read receive buffer register 0 (rxb0) if an overrun error has occurred. until rxb0 is read, the overrun error will persistently occur each time data is received. (3) baud rate generator control register 0 (brgc0) this register sets the serial clock of serial interface uart0. brgc0 is set by an 8-bit memory manipulation instruction. the value of this register is initialized to 00h after reset. figure 16-5 shows the format of brgc0. symbol asis0 7 0 6 0 5 0 4 0 3 0 2 pe0 1 fe0 0 ove0 r/w r after reset 00h address ff5bh 354 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud figure 16-5. format of baud rate generator control register 0 (brgc0) tps02 tps01 tsp00 selection of source clock of n 5-bit counter 000f x /2 (3.15 mhz) 1 001f x /2 2 (1.58 mhz) 2 010f x /2 3 (788 khz) 3 011f x /2 4 (394 khz) 4 100f x /2 5 (197 khz) 5 101f x /2 6 (98.4 khz) 6 110f x /2 7 (49.2 khz) 7 111f x /2 8 (24.6 khz) 8 mdl03 mdl02 mdl01 mdl00 selection of input clock k of baud rate generator 0000f sck /16 0 0001f sck /17 1 0010f sck /18 2 0011f sck /19 3 0100f sck /20 4 0101f sck /21 5 0110f sck /22 6 0111f sck /23 7 1000f sck /24 8 1001f sck /25 9 1010f sck /26 10 1011f sck /27 11 1100f sck /28 12 1101f sck /29 13 1110f sck /30 14 1111 setting prohibited caution if data is written to brgc0 during communication, the output of the baud rate generator is disturbed and communication cannot be executed normally. therefore, do not write brgc0 during communication. remark f sck : source clock of 5-bit counter n: value set by tps00 to tps02 (1 n 8) k: value set by mdl00 to mdl03 (0 k 14) ( ): f x = 6.3 mhz symbol brgc0 7 0 6 tps02 5 tps01 4 tps00 3 mdl03 2 mdl02 1 mdl01 0 mdl00 r/w r/w after reset 00h address ff5ch 355 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud 16.4 operation of serial interface uart0 this section explains the two modes of serial interface uart0. 16.4.1 operation stop mode in this mode, serial transfer is not performed, and the pins used for the serial interface can be used as ordinary port pins. (1) register setting the operation stop mode is set using asynchronous serial interface mode register 0 (asim0). asim0 is set by a 1-bit or 8-bit memory manipulation instruction. the value of this register is initialized to 00h after reset. txe0 rxe0 operating mode function of rxd0/p74 pin function of txd0/p75 pin 0 0 operation stop port function (p74) port function (p75) 0 1 uart mode (reception only) serial function (rxd0) 1 0 uart mode (transmission only) port function (p74) serial function (txd0) 1 1 uart mode serial function (rxd0) (transmission/reception) note be sure to reset bit 0 of asim0 to 0. caution before changing the operating mode, stop the serial transmission/reception operation. symbol asim0 <7> txe0 <6> rxe0 5 ps01 4 ps00 3 cl0 2 sl0 1 isrm0 0 0 note r/w r/w after reset 00h address ff5ah 356 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud 16.4.2 asynchronous serial interface (uart) mode this mode is used to transmit or receive 1-byte data following a start bit. full duplex operation can be executed in this mode. because a uart-dedicated baud rate generator is provided, communication can be executed at a wide range of baud rates. moreover, the baud rate of the midi standard (31.25 kbps) can also be generated by using the uart-dedicated baud rate generator. (1) register setting the uart mode is set using asynchronous serial interface mode register 0 (asim0), asynchronous serial interface status register 0 (asis0), baud rate generator control register 0 (brgc0), port mode register 7 (pm7), and port 7 (p7). (a) asynchronous serial interface mode register 0 (asim0) asim0 is set by a 1-bit or 8-bit memory manipulation instruction. the value of this register is initialized to 00h after reset. 357 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud txe0 rxe0 operating mode function of rxd0/p74 pin function of txd0/p75 pin 0 0 operation stop port function (p74) port function (p75) 0 1 uart mode (reception only) serial function (rxd0) 1 0 uart mode (transmission only) port function (p74) serial function (txd0) 1 1 uart mode serial function (rxd0) (transmission/reception) ps01 ps00 specifion of parity bit 0 0 no parity 0 1 0 parity always appended during transmission. parity not checked during reception (parity error does not occur). 1 0 odd parity 1 1 even parity cl0 specification of character length 0 7 bits 1 8 bits sl0 specification of stop bit length of transmit data 0 1 bit 1 2 bits isrm0 control of reception completion interrupt in case of error 0 reception completion interrupt request generated in case of error 1 reception completion interrupt request not generated in case of error note be sure to reset bit 0 of asim0 to 0. cautions 1. before changing the operation mode, stop the serial transmission/reception operation. 2. set port mode register 7 (pm7) and the output latch of port 7 (p7) as follows in the uart mode. during reception set p74 (rxd0) to the input mode (pm74 = 1). during transmission set p75 (txd0) to the output mode (pm75 = 0, p75 = 0). during transmission/reception set p74 to the input mode and p75 to the output mode. symbol asim0 <7> txe0 <6> rxe0 5 ps01 4 ps00 3 cl0 2 sl0 1 isrm0 0 0 note r/w r/w after reset 00h address ff5ah 358 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud (b) asynchronous serial interface status register 0 (asis0) asis0 is set by an 8-bit memory manipulation instruction. the value of this register is initialized to 00h after reset. pe0 parity error flag 0 no parity error 1 parity error occurred (if parity of transmit data did not match). fe0 framing error flag 0 no framing error 1 framing error occurred note 1 (if stop bit was not detected). ove0 overrun error flag 0 no overrun error 1 overrun error occurred note 2 (if next reception operation was completed before data was read from receive buffer register 0). notes 1. even when the stop bit length is set to 2 bits by bit 2 (sl0) of asynchronous serial interface mode register 0 (asim0), only 1 stop bit is detected during reception. 2. be sure to read receive buffer register 0 (rxb0) if an overrun error has occurred. until rxb0 is read, the overrun error will persistently occur each time data is received. 7 0 6 0 5 0 4 0 3 0 2 pe0 1 fe0 0 ove0 symbol asis0 r/w r after reset 00h address ff5bh 359 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud (c) baud rate generator control register 0 (brgc0) brgc0 is set by an 8-bit memory manipulation instruction. reset input sets brgc0 to 00h. tps02 tps01 tps00 selection of source clock n of 5-bit counter 000f x /2 (3.15 mhz) 1 001f x /2 2 (1.58 mhz) 2 010f x /2 3 (788 khz) 3 011f x /2 4 (394 khz) 4 100f x /2 5 (197 khz) 5 101f x /2 6 (98.4 khz) 6 110f x /2 7 (49.2 khz) 7 111f x /2 8 (24.6 khz) 8 mdl03 mdl02 mdl01 mdl00 selection of input clock k of baud rate generator 0000f sck /16 0 0001f sck /17 1 0010f sck /18 2 0011f sck /19 3 0100f sck /20 4 0101f sck /21 5 0110f sck /22 6 0111f sck /23 7 1000f sck /24 8 1001f sck /25 9 1010f sck /26 10 1011f sck /27 11 1100f sck /28 12 1101f sck /29 13 1110f sck /30 14 1111 setting prohibited caution if data is written to brgc0 during communication, the output of the baud rate generator is disturbed and communication cannot be executed normally. therefore, do not write brgc0 during communication. remark f sck : source clock of 5-bit counter n: value set by tps00 to tps02 (1 n 8) k: value set by mdl00 to mdl03 (0 k 14) ( ): f x = 6.3 mhz 7 0 6 tps02 5 tps01 4 tps00 3 mdl03 2 mdl02 1 mdl01 0 mdl00 symbol brgc0 r/w r/w after reset 00h address ff5ch 360 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud (2) baud rate the baud rate can be calculated by the following expression. [baud rate] = f x [bps] 2 n+1 (k + 16) f x : system clock oscillation frequency n: value set by tps00 to tps02 (1 n 8) (refer to figure 16-5.) k: value set by mdl00 to mdl03 (0 k 14) (refer to figure 16-5.) table 16-2. brgc0 set value for each baud rate target baud rate f x = 6.3 mhz f x = 4.5 mhz [bps] brgc0 error (%) brgc0 error (%) 300 7dh 1.02 600 75h 2.34 6dh 1.02 1200 65h 2.34 5dh 1.02 2400 55h 2.34 4dh 1.02 4800 45h 2.34 3dh 1.02 9600 35h 2.34 2dh 1.02 19200 25h 2.34 1dh 1.02 31250 19h 0.8 12h 0.0 38400 15h 2.34 0dh 1.02 remark baud rate = f x /{2 n+1 (k + 16)} f x : system clock oscillation frequency n: value set by tps00 to tps02 (1 n 8) k: value set by mdl00 to mdl03 (0 k 14) 361 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud permissible error range of baud rate the error of the baud rate depends on the number of bits in one frame and the division ratio of the 5-bit counter [1/(16 + k)]. figure 16-5 shows an example of the permissible error. figure 16-6. permissible error of baud rate allowing for sampling error (k = 0) permissible baud rate error (where k = 0) = 15.5 100 = 4.8438 (%) 320 caution the above permissible error value is the calculated value based on the ideal sampling point. when designing, take the error of the start bit detection time into consideration and add margins. remark t: source clock cycle of 5-bit counter 32t 64t 256t 288t ideal sampling point 320t 352t reference timing high-speed limit timing low-speed limit timing start start start d0 d7 p 304t 336t stop 15.5t stop p d7 d0 30.45t 60.9t 304.5t d0 d7 p 33.55t 67.1t 301.95t 335.5t stop sampling error 0.5t 15.5t 362 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud (3) basic operation (a) data format figure 16-7 shows the format of the transmit/receive data. figure 16-7. format of transmit/receive data of asynchronous serial interface one data frame consists of the following bits. start bit .............. 1 bit character bits .... 7 or 8 bits (lsb-first) parity bit ............. even parity/odd parity/0 parity/no parity stop bit .............. 1 or 2 bits the character bit length, parity, and stop bit length of one data frame are selected by asynchronous serial interface mode register 0 (asim0). if the character bit length is specified to be 7 bits, only the lower 7 bits (bits 0 to 6) are valid. the most significant bit (bit 7) is ignored during transmission, and it is 0 during reception. the serial transfer rate is set by baud rate generator control register 0 (bgrc0). if a receive error occurs in the serial data, the error can be identified by reading the status of asynchronous serial interface status register 0 (asis0). (b) type and operation of parity a parity bit is used to detect a bit error in the communication data. usually, the same type of parity bit is used on both the transmitter and receiver sides. with even parity or odd parity, an error of 1 bit (or odd-number error) can be detected. errors cannot be detected when 0 parity or no parity is specified. 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit character bits 363 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud (i) even parity during transmission the parity bit is set so that the number of bits in the transmit data, plus the parity bit, that are 1 is even. the value of the parity bit is as follows. if the number of bits in transmit data that are 1 is odd: 1 if the number of bits in transmit data that are 1 is even: 0 during reception the number of bits in the receive data, including the parity bit, that are 1 are counted. if the number of bits is odd, a parity error occurs. (ii) odd parity during transmission the parity bit is set so that the number of bits in the transmit data, plus the parity bit, that are 1 is odd. the value of the parity bit is as follows. if the number of bits in transmit data that are 1 is odd: 0 if the number of bits in transmit data that are 1 is even: 1 during reception the number of bits in the receive data, including the parity bit, that are 1 are counted. if the number of bits is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 during transmission, regardless of the transmit data. the parity bit is not checked during reception. therefore, a parity error does not occur regardless of whether the parity bit is 0 or 1. (iv) no parity a parity bit is not appended to the transmit data. during reception, data is received assuming that it has no parity bit. because no parity bit is used, parity errors do not occur. 364 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud (c) transmission the transmission operation is started when transmit data is written to transmit shift register 0 (txs0). the start bit, parity bit, and stop bit are automatically appended. when the data in txs0 is shifted out and txs0 becomes empty as a result of starting transmission, a transmission completion interrupt request (intst0) is generated. figure 16-8 shows the timing of the transmission completion interrupt. figure 16-8. generation timing of transmission completion interrupt request of asynchronous serial interface (i) stop bit length: 1 (ii) stop bit length: 2 caution do not change the contents of asynchronous serial interface mode register 0 (asim0) during transmission. if the contents of the asim0 register are changed during transmission, subsequent transmissions may not be able to be performed (the normal status can be restored by reset input). whether transmission is in progress can be checked by software, by using the transmission completion interrupt request (intst0) or the interrupt request flag (stif0) that is set by intst0. txd0 (output) intst0 d0 start d1 d2 d6 d7 parity stop txd0 (output) intst0 d0 start d1 d2 d6 d7 parity stop 365 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud (d) reception reception is enabled when bit 6 (rxe0) of asynchronous serial interface mode register 0 (asim0) is set to 1, and then the input to the rxd0 pin is sampled. the rxd0 pin is sampled with the serial clock specified by asim0. when the rxd0 pin goes low, the 5-bit counter of the baud rate generator starts counting. when a time of half the set baud rate has elapsed, the start timing signal of data sampling is output. if the rxd0 pin is sampled with this start timing signal again and is found to be low level, the pin level is recognized as a start bit. the 5-bit counter is initialized, counting is started, and the data is sampled. if character data, a parity bit, and 1 stop bit are detected after the start bit, reception of one frame of data is completed. when reception of one frame of data has been completed, the receive data in the shift register is transferred to receive buffer register 0 (rxb0), and a reception completion interrupt request (intsr0) is generated. even if an error occurs, the receive data in which the error occurred is transferred to rxb0. if bit 1 (isrm0) of asim0 is cleared to 0 when the error occurred, intsr0 is generated (refer to figure 16-10). intsr0 is not generated if the isrm0 bit is set to 1. if the rxe0 bit is reset to 0 during reception, reception is immediately stopped. at this time, the contents of rxb0 and asis0 are not affected, nor are intsr0 and intser0 generated. figure 16-9 shows the timing of generating the reception completion interrupt request of the asynchronous serial interface. figure 16-9. timing of generation of reception completion interrupt of asynchronous serial interface caution be sure to read receive buffer register 0 (rxb0) even if a reception error occurs. otherwise, an overrun error occurs when the next data is received, and the reception error status persists. rxd0 (input) intsr0 d0 start d1 d2 d6 d7 parity stop 366 chapter 16 serial interface uart0 ( pd178076, 178078, and 178f098 only) user s manual u12790ej2v0ud (e) reception error three types of errors: a parity error, framing error, and overrun error, may occur during reception. if the error flag in asynchronous serial interface status register 0 (asis0) is set as a result of receiving data, the reception error interrupt request (intser0) is generated. this interrupt occurs before the reception completion interrupt request (intsr0). table 16-3 shows the causes of reception errors. which error has occurred during reception can be identified by reading the contents of asis0 in the reception error processing (intser0) (refer to table 16-3 and figure 16-10). the contents of asis0 are reset when receive buffer register 0 (rxb0) is read or the next data is received (if an error occurs in the next data, the corresponding error flag is set). table 16-3. causes of reception errors reception error cause value of asis0 parity error parity specified for transmission does not match parity of receive data. 04h framing error stop bit is not detected. 02h overrun error reception of next data is completed before data is read from receive buffer register 0. 01h figure 16-10. reception error timing note if a reception error occurs while the isrm0 bit is set to 1, intsr0 does not occur. cautions 1. the contents of asynchronous serial interface status register 0 (asis0) are reset to 0 when receive buffer register 0 (rxb0) is read or the next data is received. to identify the error, be sure to read asis0 before reading rxb0. 2. be sure to read receive buffer register 0 (rxb0) even if a reception error occurs. otherwise, an overrun error occurs when the next data is received, and the reception error status persists. rxd0 (input) intsr0 note d0 start d1 d2 d6 d7 parity stop intser0 (if framing/overrun error occurs) intser0 (if parity error occurs) 367 user? manual u12790ej2v0ud chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) the pd178098a subseries ( pd178096a, 178098a, 178f098) incorporates an iebus controller. iebus (inter equipment bus) is a small-scale digital data transfer system that transfers data between units. to implement iebus by using the pd178098a subseries, an external iebus driver and receiver are necessary because they are not provided. the internal iebus controller of the pd178098a subseries is of negative logic. 17.1 iebus controller functions 17.1.1 communication protocol of iebus the communication protocol of the iebus is as follows. (1) multitask mode all the units connected to the iebus can transfer data to the other units. (2) broadcast communication function communication between one unit and multiple units can be performed as follows. ? group-unit broadcast communication: broadcast communication to group units ? all-unit broadcast communication: broadcast communication to all units (3) effective transfer rate the effective transfer rate is in mode 1 (the pd178098a subseries does not support modes 0 and 2 for the effective transfer rate). ? mode 1: approx. 18 kbps (when f x = 6.3 mhz) caution different modes must not be mixed on one iebus. (4) communication mode data transfer is executed in half-duplex asynchronous communication mode. (5) access control: csma/cd (carrier sense multiple access with collision detection) the priority of the iebus is as follows. <1> broadcast communication takes precedence over individual communication (communication from one unit to another). <2> the lower master address takes precedence. (6) communication scale the communication scale of iebus is as follows. ? number of units: 50 max. ? cable length: 150 m max. (when twisted pair cable is used) caution the communication scale in an actual system differs depending on the characteristics of the cables, etc., constituting the iebus driver/receiver and iebus. 368 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user? manual u12790ej2v0ud 17.1.2 determination of bus mastership (arbitration) an operation to occupy the bus is performed when a unit connected to the iebus controls the other units. this operation is called arbitration. when two or more units simultaneously start transmission, arbitration is used to grant one of the units permission to occupy the bus. because only one unit is granted the bus mastership as a result of arbitration, the priority conditions of the bus are predetermined as follows. caution the bus mastership is released if communication is aborted. (1) priority by communication type broadcast communication (communication from one unit to multiple units) takes precedence over normal communication (communication from one unit to another). (2) priority by master address if the communication type is the same, communication with the lower master address takes precedence. a master address consists of 12 bits, with unit 000h having the highest priority and unit fffh having the lowest priority. 17.1.3 communication mode although the iebus has three communication modes each having a different transfer rate, the pd178098a subseries supports only communication mode 1. the transfer rate and the maximum number of transfer bytes in one communication frame in communication mode 1 are as shown in table 17-1. table 17-1. transfer rate and maximum number of transfer bytes in communication mode 1 communication mode maximum number of transfer bytes (bytes/frame) effective transfer rate (kbps) note 1 32 approx. 18 note the effective transfer rate when the maximum number of transfer bytes is transmitted (when f x = 6.3 mhz). select the communication mode (mode 1) for each unit connected to the iebus before starting communication. if the communication mode of the master unit and that of the partner unit (slave unit) are not the same, communication is not executed correctly. 17.1.4 communication address with the iebus, each unit is assigned a specific 12-bit address. this communication address consists of the following identification numbers. ? higher 4 bits: group number (number to identify the group to which each unit belongs) ? lower 8 bits: unit number (number to identify each unit in a group) 369 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user? manual u12790ej2v0ud 17.1.5 broadcast communication normally, transmission or reception is performed between the master unit and its partner slave unit on a one-to-one basis. during broadcast communication, however, two or more slave units exist and the master unit executes transmission to these slave units. because multiple slave units exist, the slave units do not return an acknowledge signal during communication. whether broadcast communication or normal communication is to be executed is selected by the broadcast bit (for this bit, refer to 17.1.6 (2) broadcast bit ). broadcast communication is classified into two types: group-unit broadcast communication and all-unit broadcast communication. group-unit broadcast and all-unit broadcast are identified by the value of the slave address (for the slave address, refer to 17.1.6 (4) slave address field ). (1) group-unit broadcast communication broadcast communication is performed with the units in a group identified by the group number indicated by the higher 4 bits of the communication address. (2) all-unit broadcast communication broadcast communication is performed with all the units, regardless of the value of the group number. 17.1.6 transfer format of iebus caution the logic on the iebus i/o pin of the pd178098a subseries and the logic of the iebus protocol (data on the iebus) are inverted values. the following describes the case of the iebus protocol. 370 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (2) broadcast bit this bit indicates whether the master selects one slave (individual communication) or multiple slaves (broadcast communication) as the other party of communication. when the broadcast bit is 0, it indicates broadcast communication; when it is 1, individual communication is indicated. broadcast communication is classified into two types: group-unit communication and all-unit communication. these communication types are identified by the value of the slave address (for the slave address, refer to 17.1.6 (4) slave address field ). because two or more slave units exist in the case of broadcast communication, the acknowledge bit in each field subsequent to the master address field is not returned. if two or more units start transmitting a communication frame at the same time, broadcast communication takes precedence over individual communication, and wins in arbitration. if one unit occupies the bus as the master, the value set to the broadcast request flag (allrq) of iebus control register 0 (bcr0) is output. (3) master address field the master address field is output by the master to inform a slave of the master s address. the configuration of the master address field is as shown in figure 17-2. if two or more units start transmitting the broadcast bit at the same time, the master address field is used to make a judgment of arbitration. the data output in the master address field is compared with the data on the bus each time one bit is output. if the master address output in the master address field is found to be different from the data on the bus as a result of comparison, it is assumed that the master has lost in arbitration. as a result, the master stops transmission and enters the reception status. because the iebus is configured of wired and, the unit having the minimum master address of the units participating in arbitration (arbitration masters) wins in arbitration. after a 12-bit master address has been output, only one unit remains in the transmission status as the master unit. next, this master unit outputs a parity bit, determines the master address of other units, and starts outputting a slave address field. if one unit occupies the bus as the master, the address set by the iebus unit address register (uar) is output. figure 17-2. master address field master address field master address (12 bits) msb lsb parity 371 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (4) slave address field the master outputs the address of the unit with which it is to communicate. figure 17-3 shows the configuration of the slave address field. a parity bit is output after a 12-bit slave address has been transmitted in order to prevent a wrong slave address from being received by mistake. next, the master unit detects an acknowledge signal from the slave unit to confirm that the slave unit exists on the bus. when the master has detected the acknowledge signal, it starts outputting the control field. during broadcast communication, however, the master does not detect the acknowledge bit but starts outputting the control field. the slave unit outputs the acknowledge signal if its slave address matches and if the slave detects that the parities of both the master address and slave address are even. the slave unit judges that the master address or slave address has not been correctly received and does not output the acknowledge signal if the parities are odd. at this time, the master unit is in the standby (monitor) status, and communication ends. during broadcast communication, the slave address is used to identify group-unit broadcast or all-unit broadcast, as follows. if slave address is fffh: all-unit broadcast communication if slave address is other than fffh: group-unit broadcast communication remark the group no. during group-unit broadcast communication is the value of the higher 4 bits of the slave address. if one unit occupies the bus as the master, the address set by the iebus slave address register (sar) is output. figure 17-3. slave address field slave address field unit no. msb lsb ack parity slave address (12 bits) group no. (5) control field the master outputs the operation it requires the slave to perform, by using this field. the configuration of the control field is as shown in figure 17-4. if the parity following the control bit is even and if the slave unit can execute the function required by the master unit, the slave unit outputs an acknowledge signal and starts outputting the telegraph length field. if the slave unit cannot execute the function required by the master unit even if the parity is even, or if the parity is odd, the slave unit does not output the acknowledge signal, and returns to the standby (monitor) status. the master unit starts outputting the telegraph field after confirming the acknowledge signal. if the master cannot confirm the acknowledge signal, the master unit enters the standby status, and communication ends. during broadcast communication, however, the master unit does not confirm the acknowledge signal, and starts outputting the telegraph length field. table 17-2 shows the contents of the control bits. 372 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud table 17-2. contents of control bits bit 3 note 1 bit 2 bit 1 bit 0 function 0 0 0 0 read slave status 0 0 0 1 undefined 0 0 1 0 undefined 0 0 1 1 read data and lock note 2 0 1 0 0 read lock address (lower 8 bits) note 3 0 1 0 1 read lock address (higher 4 bits) note 3 0 1 1 0 read slave status and unlock note 2 0 1 1 1 read data 1 0 0 0 undefined 1 0 0 1 undefined 1 0 1 0 write command and lock note 2 1 0 1 1 write data and lock note 2 1 1 0 0 undefined 1 1 0 1 undefined 1 1 1 0 write command 1 1 1 1 write data notes 1. the telegraph length bit of the telegraph length field and data transfer direction of the data field change as follows depending on the value of bit 3 (msb). if bit 3 is 1 : transfer from master unit to slave unit if bit 3 is 0 : transfer from slave unit to master unit 2. this is a control bit that specifies locking or unlocking (refer to 17.1.7 (4) locking and unlocking ). 3. the lock address is transferred in 1-byte (8-bit) units and is configured as follows. msb lower 8 bits undefined higher 4 bits control bit: 4h control bit: 5h lsb 373 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud if the control bit received from the master unit is not as shown in table 17-3, the unit locked by the master unit rejects acknowledging the control bit, and does not output the acknowledge bit. table 17-3. control field for locked slave unit bit 3 bit 2 bit 1 bit 0 function 0 0 0 0 read slave status 0 1 0 0 read lock address (lower 8 bits) 0 1 0 1 read lock address (higher 4 bits) moreover, units for which lock is not set by the master unit reject acknowledgment and do not output an acknowledge bit when the control data shown in table 17-4 is acknowledged. table 17-4. control field for unlocked slave unit bit 3 bit 2 bit 1 bit 0 function 0 1 0 0 read lock address (lower 8 bits) 0 1 0 1 read lock address (higher 4 bits) if one unit occupies the bus as the master, the value set to the iebus control data register (cdr) is output. figure 17-4. control field msb lsb ack parity control bit (4 bits) control field 374 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud table 17-5. acknowledge signal output conditions of control field (a) if received control data is ah, bh, eh, or fh communication lock status master unit slave slave reception received control data target (slvrq) (lock) identification transmission enable ah bh eh fh slave lock = 1 (match with par) enable (enslvrx) specification = 1 unlock = 0 lock request (enslvtx) no specification unit = 1 = 0 other = 0 1 0 don t care don t care 1 11 other than above (b) if received control data is 0h, 3h, 4h, 5h, 6h, or 7h communication lock status master unit slave slave reception received control data target (slvrq) (lock) identification transmission enable 0h 3h 4h 5h 6h 7h slave lock = 1 (match with par) enable (enslvrx) specification = 1 unlock = 0 lock request (enslvtx) no specification unit = 1 = 0 other = 0 1 0 don t care 0 don t care ?? 1 ??? 1 0 don t care ??? 10 ???? 1 ????? other than above caution if the received control data is other than the data shown in table 17-5, (ack is not returned) is unconditionally assumed. remarks 1. : ack is returned. : ack is not returned. 2. enslvtx: bit 4 of iebus control register 0 (bcr0) enslvrx: bit 3 of iebus control register 0 (bcr0) lock: bit 2 of the iebus unit status register (usr) slvrq: bit 6 of the iebus unit status register (usr) par: iebus partner address register 375 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (6) telegraph length field this field is output by the transmission side to inform the reception side of the number of bytes of the transmit data. the configuration of the telegraph length field is as shown in figure 17-5. table 17-6 shows the relationship between the telegraph length bit and the number of transmit data. figure 17-5. telegraph length field msb lsb telegraph length field telegraph length bit (8 bits) parity ack table 17-6. contents of telegraph length bit telegraph length bit (hex) number of transmit data bytes 01h 1 byte 02h 2 bytes || ffh 255 bytes 00h 256 bytes the operation of the telegraph length field differs depending on whether the master transmits data (when control bit 3 is 1) or receives data (when control bit 3 is 0). (a) when master transmits data the telegraph length bit and parity bit are output by the master unit. when the slave unit detects that the parity is even, it outputs the acknowledge signal, and starts outputting the data field. during broadcast communication, however, the slave unit does not output the acknowledge signal. if the parity is odd, the slave unit judges that the telegraph length bit has not been correctly received, does not output the acknowledge signal, and returns to the standby (monitor) status. at this time, the master unit also returns to the standby status, and communication ends. (b) when master receives data the telegraph length bit and parity bit are output by the slave unit and the synchronization signals of bits are output by the master unit. if the master unit detects that the parity bit is even, it outputs the acknowledge signal. if the parity bit is odd, the master unit judges that the telegraph length bit has not been correctly received, does not output the acknowledge signal, and returns to the standby (monitor) status. at this time, the slave unit also returns to the standby status, and communication ends. 376 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (7) data field this is data output by the transmission side. the master unit transmits to or receives data from a slave unit by using the data field. the configuration of the data field is as shown below. figure 17-6. data field data field (number specified by telegraph length field) msb lsb one data ack parity control bit (8 bits) ack parity following the data bit, the parity bit and acknowledge bit are respectively output by the master unit and slave unit. use broadcast communication only for when the master unit transmits data. at this time, the acknowledge bit is ignored. the operation differs as follows depending on whether the master transmits or receives data. (a) when master transmits data when the master unit writes data to a slave unit, the master unit transmits the data bit and parity bit to the slave unit. if the parity is even and the receive data is not stored in the iebus data register (dr) when the slave unit has received the data bit and parity bit, the slave unit outputs an acknowledge signal. if the parity is odd or if the receive data is stored in the iebus data register (dr), the slave unit rejects receiving the data, and does not output the acknowledge signal. if the slave unit does not output the acknowledge signal, the master unit transmits the same data again. this operation continues until the master detects the acknowledge signal from the slave unit, or the data exceeds the maximum number of transmit bytes. if there is more data and the maximum number of transmit bytes is not exceeded when the parity is even and when the slave unit outputs the acknowledge signal, the master unit transmits the next data. during broadcast communication, the slave unit does not output the acknowledge signal, and the master unit transfers 1 byte of data at a time. if the parity is odd or the dr register is storing receive data after the slave unit has received the data bit and parity bit during broadcast communication, the slave unit judges that reception has not been performed correctly, and stops reception. 377 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (b) when master receives data when the master unit reads data from a slave unit, the master unit outputs a sync signal corresponding to all the read bits. the slave unit outputs the contents of the data and parity bits to the bus in response to the sync signal from the master unit. the master unit reads the data and parity bits output by the slave unit, and checks the parity. if the parity is odd, or if the dr register is storing a receive data, the master unit rejects accepting the data, and does not output the acknowledge signal. if the maximum number of transmit bytes is within the value that can be transmitted in one communication frame, the master unit repeats reading the same data. if the parity is even and the dr register is not storing a receive data, the master unit accepts the data and returns the acknowledge signal. if the maximum number of transmit bytes is within the value that can be transmitted in one frame, the master unit reads the next data. caution do not operate master reception in broadcast communication, because the slave unit cannot be defined and data transfer cannot be performed correctly. (8) parity bit the parity bit is used to check that if the transmit data has no error. the parity bit is appended to each data of the master address, slave address, control, telegraph length, and data bits. the parity bit is even parity. if the number of bits in data that are 1 is odd, the parity bit is 1 . if the number of bits in the data that are 1 is even, the parity bit is 0 . (9) acknowledge bit during normal communication (communication from one unit to another), an acknowledge bit is appended to the following locations to check that the data has been correctly received. ? end of slave address field ? end of control field ? end of telegraph length field ? end of data field the definition of the acknowledge bit is as follows. ? 0: indicates that the transmit data is recognized (ack). ? 1: indicates that the transmit data is not recognized (nack). during broadcast communication, however, the contents of the acknowledge bit are ignored. 378 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user? manual u12790ej2v0ud (a) acknowledge bit at end of slave address field the acknowledge bit at the end of the slave address field serves as nack in any of the following cases, and transmission is stopped. ? if the parity of the master address bit or slave address bit is incorrect ? if a timing error (error in bit format) occurs ? if a slave unit does not exist (b) acknowledge bit at end of control field the acknowledge bit at the end of the control field serves as nack in any of the following cases, and transmission is stopped. ? if the parity of the control bit is incorrect ? if control bit 3 is ??(write operation) when the slave reception enable flag (enslvrx) is not set (1) (refer to 17.4.2 (1) iebus control register 0 (bcr0) ) ? if the control bit indicates reading of data (3h or 7h) when the slave transmission enable flag (enslvtx) is not set (1) (refer to 17.4.2 (1) iebus control register 0 (bcr0) ) ? if a unit other than the one that set locking requests control bits 3h, 6h, 7h, ah, bh, eh, or fh when locking is set ? if the control bit indicates reading of a lock address (4h or 5h) even when locking is not set ? if a timing error occurs ? if the control bit is undefined cautions 1. even when the slave transmission enable flag (enslvtx) is not set (1), ack may be returned if control data is received (refer to table 17-5). 2. even when the slave reception enable flag (enslvrx) is not set (1), nack is always returned by the acknowledge bit in the control field if data/command writing control data is acknowledged. slave reception can be disabled (communication stopped) by the enslvrx flag only in the case of individual communication. in the case of broadcast communication, communication is maintained and the data request interrupt (intie1) or iebus end interrupt (intie2) is generated. 379 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (c) acknowledge bit at end of telegraph length field the acknowledge bit at the end of the telegraph length field serves as nack in any of the following cases, and transmission is stopped. ? if the parity of the telegraph length bit is incorrect ? if a timing error occurs (d) acknowledge bit at end of data field the acknowledge bit at the end of the data field serves as nack in any of the following cases, and transmission is stopped. ? if the parity of the data bit is incorrect note ? if a timing error occurs after the preceding acknowledge bit has been transmitted ? if receive data is stored in the iebus data register (dr) and no more data can be received note note in this case, when the communication executed is individual communication, if the maximum number of transmit bytes is within the value that can be transmitted in one frame, the transmission side executes transmission of that data field again. for broadcast communication, the transmission side does not execute transmission again, a communication error occurs on the reception side and reception stops. 17.1.7 transfer data (1) slave status the master unit can learn why the slave unit did not return the acknowledge bit (ack) by reading the slave status. the slave status is determined according to the result of the last communication the slave unit has executed. all the slave units can supply information on the slave status. the configuration of the slave status is shown below. 380 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud figure 17-7. bit configuration of slave status bit 7 transmit data is not written in iebus data register (dr) transmit data is written in iebus data register (dr) bit 0 note 1 0 1 meaning bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 msb lsb receive data is not stored in iebus data register (dr) receive data is stored in iebus data register (dr) bit 1 note 2 0 1 meaning unit is not locked unit is locked bit 2 0 1 meaning fixed to 0 bit 3 0 meaning fixed to 0 bit 5 0 meaning meaning bit 7 0 0 1 1 mode 0 mode 1 mode 2 not used indicates the highest mode supported by unit note 4 . bit 6 0 1 0 1 slave transmission is stopped slave transmission is ready bit 4 note 3 0 1 meaning notes 1. after reset: bit 0 is set to 1. 2. the receive buffer size is 1 byte. 3. when the pd178098a subseries serves as a slave unit, this bit corresponds to the status indicated by bit 4 (enslvtx) of iebus control register 0 (bcr0). 4. when the pd178098a subseries serves as a slave unit, bits 7 and 6 are fixed to 0 and 1 (mode 1), respectively. 381 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (2) lock address when the lock address is read (control bit: 4h or 5h), the address (12 bits) of the master unit that has issued the lock instruction is configured in 1-byte units as shown below and read. figure 17-8. configuration of lock address msb lower 8 bits undefined higher 4 bits control bit: 4h control bit: 5h lsb (3) data if the control bit indicates reading of data (3h or 7h), the data in the data buffer of the slave unit is read by the master unit. if the control bit indicates writing of data (bh or fh), the data received by the slave unit is processed according to the operation rule of that slave unit. (4) locking and unlocking the lock function is used when a message is transferred in two or more communication frames. the unit that is locked does not receive data from units other than the one that has locked the unit (either individual or broadcast communication). a unit is locked or unlocked as follows. (a) locking if the communication frame is completed without succeeding to transmit or receive data of the number of bytes specified by the telegraph length bit after the telegraph length field has been transmitted or received (ack = 0) by the control bit that specifies locking (3h, ah, or bh), the slave unit is locked by the master unit. at this time, the bit (bit 2) in the byte indicating the slave status is set to 1 . (b) unlocking after transmitting or receiving data of the number of data bytes specified by the telegraph length bit in one communication frame by the control bit that has specified locking (3h, ah, or bh), or the control bit that has specified unlocking (6h), the slave unit is unlocked by the master unit. at this time, the bit related to locking (bit 2) in the byte indicating the slave status is reset to 0 . locking or unlocking is not performed during broadcast communication. the locking and unlocking conditions are shown below. 382 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (c) lock setting conditions control data broadcast communication individual communication communication end frame end communication end frame end 3h, 6h note not locked lock set ah, bh not locked not locked not locked lock set 0h, 4h, 5h, eh, fh not locked not locked not locked not locked (d) lock release conditions (while locked) control data broadcast communication from lock request unit individual communication from lock request unit communication end frame end communication end frame end 3h, 6h note unlocked remains locked ah, bh unlocked unlocked unlocked remains locked 0h, 4h, 5h, eh, fh remains locked remains locked remains locked remains locked note the frame end of control data 6h (slave status read/unlock) occurs when the parity in the data field is odd, and when the acknowledge signal from the iebus unit is repeated up to the maximum number of transfer bytes without being output. 17.1.8 bit format caution the logic on the iebus i/o pin of the pd178098a subseries and the logic of the iebus protocol (data on the iebus) are inverted values. the following describes the case of the iebus protocol. 383 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud notes 1. the pd178098a subseries supports the iebus controller when f x = 6.3 mhz. when f x = 4.5 mhz, the iebus controller is not supported. 2. automatic master reprocessing: after generating the master request, if the master request is cancelled by arbitration, etc., the bus is released and the master automatically re-issues the master request. communication start preprocessing (data setting) setting and management of each communication status writing data to transmit buffer reading data from receive buffer bit processing (modulation/demodulation, error detection) field processing (generation/management) arbitration result detection parity processing (generation/error detection) automatic return of ack/nack automatic data reprocessing automatic master reprocessing note 2 transmission processing such as automatic slave status transmission multiple-frame reception processing 17.2 simple iebus controller the pd178098a subseries has a newly developed iebus controller. the functions of this iebus controller are limited compared with the conventional iebus interface functions of the existing models (provided in the 78k/0 series). table 17-7 compares the conventional iebus interface functions of the existing models with the simple iebus interface functions of the pd178098a subseries. table 17-7. comparison of existing and simple iebus interface functions item conventional functions (iebus of 78k/0) simple version (iebus incorporated in pd178098a subseries) communication mode modes 0, 1, and 2 fixed to mode 1 internal system clock f x = 6.0 (6.29) mhz f x = 6.3 mhz note 1 internal buffer size transmit buffer: 33 bytes (fifo) transmit/receive data register receive buffer: 40 bytes (fifo) up to 4 frames can be received. cpu processing hardware processing communication start preprocessing (data setting) setting and management of each communication status 1-byte data write processing 1-byte data read processing management of transmission such as slave status management of multiple frames, master request reprocessing bit processing (modulation/demodulation, error detection) field processing (generation/management) arbitration result detection parity processing (generation/error detection) automatic return of ack/nack automatic data transmission reprocessing 384 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud 17.3 iebus controller configuration the block diagram of the iebus controller is shown below. figure 17-10. iebus controller block diagram bcr0(8) uar ( 12 ) sar ( 12 ) par ( 12 ) cdr ( 8) dlr ( 8) dr ( 8 ) usr(8 ) isr ( 8 ) ssr(8 ) scr(8 ) ccr(8 ) 81212 888 8 12 888 888 888 88 8 nf rx0 mpx mpx 12-bit latch comparator conflict detection ack generation parity generation error detection tx/rx interrupt controller interrupt control block int request cpu interface block internal registers iebus interface block clk bit processing block field processing block internal bus r/w psr (8 bits) 8 5 8 12 12 12 internal bus 8 12 tx0/p120 pm120 p120 output latch 385 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (1) hardware configuration and functions the iebus mainly consists of the following six internal blocks. ? cpu interface block ? interrupt control block ? internal registers ? bit processing block ? field processing block ? iebus interface block (a) cpu interface block this is a control block that interfaces between the cpu and the iebus. (b) interrupt control block this control block transfers interrupt request signals from the iebus to the cpu. (c) internal registers these registers set data to the control registers and fields that control the iebus (for the internal registers, refer to 17.4 internal registers of iebus controller ). (d) bit processing block this block generates and disassembles bit timing, and mainly consists of a bit sequence rom, 8-bit preset timer, and comparator. (e) field processing block this block generates each field in the communication frame, and mainly consists of a field sequence rom, 4-bit down counter, and comparator. (f) iebus interface block this is the interface block for an external driver/receiver, and mainly consists of a noise filter, shift register, conflict detector, parity detector, parity generator, and ack/nack generator. 386 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud 17.4 internal registers of iebus controller 17.4.1 internal register list table 17-8. internal registers of iebus controller address function register name symbol r/w bit units for manipulation after 1 bit 8 bits 16 bits reset ffb0h iebus control register 0 bcr0 r/w ?? 00h ffb2h iebus unit address register uar ?? 0000h ffb4h iebus slave address register sar ?? ffb6h iebus partner address register par r ?? ffb8h iebus control data register cdr r/w ?? 01h ffb9h iebus telegraph length register dlr ?? ffbah iebus data register dr ?? 00h ffbbh iebus unit status register usr r ?? ffbch iebus interrupt status register isr r/w ?? ffbdh iebus slave status register ssr r ?? 41h ffbeh iebus communication success counter scr ?? 01h ffbfh iebus transmit counter ccr ?? 20h cautions 1. the above registers are mapped to the sfr space. 2. registers uar, sar, and par must be manipulated in word units. 3. instructions in read modify write mode (such as xch and rol4) cannot be used for dr, cdr, dlr, and isr. 4. when using the iebus, set port mode register 12 (pm12) and the output latch of port 12 (p12) as follows. set the p120/tx0 pin in the output mode (pm120 = 0, p120 = 0) set the p121/rx0 pin in the input mode (pm121 = 1) 387 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud 17.4.2 description of internal registers the internal registers incorporated in the iebus controller are described below. (1) iebus control register 0 (bcr0) figure 17-11. format of iebus control register 0 (bcr0) cautions 1. while the iebus is operating as the master, writing to the bcr0 register (including bit manipulation instructions) is disabled until either the end of that communication or frame, or until communication is stopped by the occurrence of an arbitration-loss communication error. master requests cannot therefore be nested. however, if the iebus is specified as a slave while a master request is being held pending, the bcr0 register can be written to at the end of communication to clear the communication end/frame end flag. this is also the case when communication has been forcibly stopped (eniebus flag = 0). 2. if a bit manipulation instruction for the bcr0 register conflicts with a hardware reset of the mstrq flag, the bcr0 register may not operate normally. the following countermeasures are recommended in this case. ? because the hardware reset is instigated in the acknowledgment period of the slave address field, be sure to observe caution 1 of (b) master request flag (mstrq) below. ? be sure to observe the caution above regarding writing to the bcr0 register. eniebus iebus unit stopped iebus unit active eniebus 0 1 communication enable flag bcr0 mstrq allrq enslvtx enslvrx 000 after reset: 00h r/w address: ffb0h iebus unit not requested as master iebus unit requested as master mstrq 0 1 master request flag individual communication requested broadcast communication requested allrq 0 1 broadcast request flag slave transmission disabled slave transmission enabled enslvtx 0 1 slave transmission enable flag slave reception disabled slave reception enabled enslvrx 0 1 slave reception enable flag < > < > < > < > < > 388 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (a) communication enable flag (eniebus)...bit 7 389 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (d) slave transmission enable flag (enslvtx)...bit 4 390 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (2) iebus unit address register (uar) this register sets the local address of an iebus unit. this register must be always set before starting communication. the unit address (12 bits) is set to bits 11 to 0. figure 17-12. format of iebus unit address register (uar) (3) iebus slave address register (sar) when a master request is issued, the value of this register is reflected in the value of the transmit data in the slave address field. this register must always be set before starting communication. the slave address (12 bits) is set to bits 11 to 0. figure 17-13. format of iebus slave address register (sar) (4) iebus partner address register (par) (a) slave unit the value of the receive data in the master address field (address of the master unit) is written to this register. if a request 4h to read the lock address (lower 8 bits) is received from the master, the cpu must read the value of this register, and write it to the lower 8 bits of the iebus data register (dr). if a request 5h to read the lock address (higher 4 bits) is received from the master, the cpu must read the value of this register and write the data of the higher 4 bits to dr. the partner address (12 bits) is set to bits 11 to 0. figure 17-14. format of iebus partner address register (par) 15 0 14 0 13 0 12 0 uar 11109876543210 after reset: 0000h r/w address: ffb2h 15 0 14 0 13 0 12 0 sar 11109876543210 after reset: 0000h r/w address: ffb4h 15 0 14 0 13 0 12 0 par 11109876543210 after reset: 0000h r address: ffb6h 391 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (5) iebus control data register (cdr) (a) master unit the data of the lower 4 bits is reflected in the data transmitted in the control field. when a master request is issued, this register must be set in advance before starting communication. (b) slave unit the data received in the control field is written to the lower 4 bits. when the status transmission flag (statusf) of the iebus interrupt status register (isr) is set, an interrupt (intie2) is issued, and each processing should be performed by software, according to the value of the lower 4 bits of cdr. figure 17-15. format of iebus control data register (cdr) cautions 1. because the slave unit must judge whether the received data is a command or data , it must read the value of this register after completing communication. 2. instructions in read modify write mode (such as xch and rol4) cannot be used for cdr. 3. if the master unit sets an undefined value, nack is returned from the slave unit, and communication is aborted. during broadcast communication, however, the master unit continues communication without recognizing ack/nack; therefore, make sure not to set an undefined value to this register during broadcast communication. 4. in the case of defeat in a bus conflict and a slave status request is received from the unit that won, the iebus telegraph length register (dlr) is fixed to 01h . therefore, when a re-request of the master follows, the appointed telegraph length must be set to dlr. 0 read slave status undefined undefined read data and lock read lock address (lower 8 bits) read lock address (higher 4 bits) read slave status and unlock read data undefined undefined write command and lock write data and lock undefined undefined write command write data cdr3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 function cdr 0 0 0 cdr3 cdr2 cdr1 cdr0 cdr2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 cdr1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 cdr0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 after reset: 01h r/w address: ffb8h 392 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (c) slave status return operation when the iebus receives a request to transfer from master to slave status (control data: 0h, 6h) or a lock address request (4h, 5h), whether ack in the control field is returned or not depends on the status of the iebus unit. (1) if 0h or 6h control data was received in the unlocked state ack returned (2) if 4h or 5h control data was received in the unlocked state ack not returned (3) if 0h, 4h, 5h or 6h control data was received in the locked state from the unit that sent the lock request ack returned (4) if 0h, 4h, or 5h control data was received in the locked state from other than the unit that sent the lock request ack returned (5) if 6h control data was received in the locked state from other than the unit that sent the lock request ack not returned in all of the above cases, the acknowledgment of a slave status or lock address request will cause the statusf flag (bit 4 of the isr register) to be set and the status interrupt request (intie2) to be generated. the generation timing is at the end of the control field parity bit (at the start of the ack bit). however, if ack is not returned, a nack error is generated after the ack bit, and communication is terminated. figure 17-16. interrupt generation timing (for (1), (3), and (4)) figure 17-17. interrupt generation timing (for (2) and (5)) intie2 l flag set by reception of 0h, 4h, 5h, 6h iebus sequence flag reset by cpu processing control field telegraph length field statusf flag internal nack flag control bits (4 bits) parity bit (1 bit) ack bit (1 bit) telegraph length bits (8 bits) intie2 flag set by reception of 0h, 4h, 5h, 6h iebus sequence flag reset by cpu processing error generated by detection of nack control field statusf flag internal nack flag control bits (4 bits) parity bit (1 bit) ack bit (1 bit) terminated by communication error 393 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud because in (4) and (5) the communication was from other than the unit that sent the lock request while the iebus was in the locked state, the start or communication complete interrupt (intie2) is not generated, even if the iebus unit is the communication target. the statusf flag (bit 4 of the iebus interrupt status register (isr)) is set and the status interrupt request (intie2) generated, however, if a slave status or lock address request is acknowledged. note that even if the same control data is received while the iebus is in the locked state, the interrupt generation timing for intie2 differs depending on whether the master unit (3) or another unit (4) is requesting the locked state. figure 17-18. timing of intie2 interrupt generation in locked state (for (4) and (5)) note the telegraph length and data modes are not set in the case of (5) because ack is not returned. remark p: parity bit, a: ack/nack bit figure 17-19. timing of intie2 interrupt generation in locked state (for (3)) remark p: parity bit, a: ack/nack bit intie2 iebus sequence status interrupt start master address (12 + p) broad- cast slave address (12 + p + a) control (4 + p + a) telegraph length note (8 + p + a) data note (8 + p + a) intie2 iebus sequence status interrupt start master address (12 + p) broad- cast slave address (12 + p + a) control (4 + p + a) telegraph length (8 + p + a) communication complete interrupt data (8 + p + a) start interrupt 394 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (6) iebus telegraph length register (dlr) (a) transmission unit (master transmission, slave transmission) the data of this register is reflected in the data transmitted in the telegraph length field and indicates the number of bytes of the transmit data. this register must be set in advance before transmission. (b) reception unit (master reception, slave reception) the receive data in the telegraph length field transmitted from the transmission unit is written to this register. remark the iebus telegraph length register consists of a write register and a read register. consequently, data written to this register cannot be read as is. the data that can be read is the data received during iebus communication. figure 17-20. format of iebus telegraph length register (dlr) cautions 1. if the master issues a request 0h, 4h, 5h, or 6h to transmit a slave status and lock address (higher 4 bits, lower 8 bits), the contents of this register are set to 01h by hardware; therefore, the cpu does not have to set this register. 2. in the case of defeat in a bus conflict and a slave status request is received from the unit that won, the iebus telegraph length register (dlr) is fixed to 01h . therefore, when a re-request of the master follows, the appointed telegraph length must be set to dlr. 3. instructions in read modify write mode (such as xch and rol4) cannot be used for dlr. 1 byte 2 bytes : 32 bytes : 255 bytes 256 bytes number of communication data bytes bit setting value 01h 02h : 20h : ffh 00h dlr 7 0 0 : 0 : 1 0 5 0 0 : 1 : 1 0 3 0 0 : 0 : 1 0 1 0 1 : 0 : 1 0 6 0 0 : 0 : 1 0 4 0 0 : 0 : 1 0 2 0 0 : 0 : 1 0 0 1 0 : 0 : 1 0 after reset: 01h r/w address: ffb9h 395 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (7) iebus data register (dr) the iebus data register (dr) sets the communication data. the communication data (8 bits) is set to bits 7 to 0. remark the iebus data register consists of a write register and a read register. consequently, data written to this register cannot be read as is. the data that can be read is the data received during iebus communication. (a) transmission unit the data (1 byte) written to the iebus data register (dr) is stored in the shift register of the iebus. it is then output from the most significant bit, and an interrupt (intie1) is issued to the cpu each time 1 byte has been transmitted. if nack is received after 1-byte data has been transmitted during individual transfer, the next data is not transferred from dr to the shift register, and the same data is retransmitted. at this time, intie1 is not generated. intie1 is issued when the iebus interface shift register stores the iebus data register (dr) value. however, when the last byte and 32nd byte (the last byte of 1 communication frame) are stored in the shift register, intie1 is not issued. (b) reception unit one byte of the data received by the shift register of the iebus interface block is stored to this register. each time 1 byte has been correctly received, an interrupt (intie1) is issued. figure 17-21. format of iebus data register (dr) cautions 1. if the next data is not set in time while the transmission unit is set, an underrun occurs, and a communication error interrupt (intie2) occurs, stopping transmission. 2. when the iebus is a receiving unit, if the reading of the data is too late for the next data reception timing, the unit will enter the overrun state. at this time, during individual communication reception, nack will be returned at the acknowledge bit of the data field, and the master unit will be requested to retransmit the data. if an overrun error occurs during broadcast communication reception, the communication error interrupt (intie2) is generated. 3. instructions in read modify write mode (such as xch and rol4) cannot be used for dr. dr after reset: 00h r/w address: ffbah 396 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (8) iebus unit status register (usr) figure 17-22. format of iebus unit status register (usr) (a) slave request flag (slvrq)...bit 6 a flag indicating whether there has been a slave request from the master. 397 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (b) arbitration result flag (arbit)...bit 5 a flag that indicates the result of arbitration. 398 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (e) lock status flag (lock)...bit 2 a flag that indicates whether the unit is locked. 399 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (9) iebus interrupt status register (isr) this register indicates the status when the iebus issues an interrupt. isr is read to generate an interrupt, after which the specified interrupt servicing is carried out. reset the isr register after reading it. until it is reset, the intie2 interrupt signal is not generated (nor held pending). to reset the isr register, reset each flag, satisfying the reset conditions in table 17-9. table 17-9. reset conditions of flags in isr register flag name reset condition processing example ieerr, startf, statusf byte write operation of isr register. any value can isr = 00h, etc. be written. endtrns, endfram set mstrq, enslvtx, or enslvrx flag. bcr0 register = 88h or enslvtx = 1, etc. caution even if 0 is written to the endtrns or endfram flag by accessing the isr register, these flags are not reset. reset them as described above. remark mstrq: bit 6 of iebus control register 0 (bcr0) enslvtx: bit 4 of iebus control register 0 (bcr0) enslvrx: bit 3 of iebus control register 0 (bcr0) 400 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud figure 17-24. format of iebus interrupt status register (isr) caution each of ieerr, startf, statusf, endtrns, and endfram are generation triggers for the interrupt request signal (intie2) (see figure 17-28 configuration of interrupt control block). because of this, if any one of these interrupt triggers has been set, no new interrupt will be generated by a subsequent trigger. clear the flag of the interrupt source by the interrupt servicing program before the next interrupt occurs. 0 no communication error communication error ieerr 0 1 communication error flag (during communication) isr ieerr startf statusf endtrns endfram 00 start interrupt does not occur start interrupt occurs startf 0 1 start interrupt flag status transmission flag (slave) after reset: 00h r/w address: ffbch no slave status/lock address (higher 4 bits, lower 8 bits) transmission request slave status/lock address (higher 4 bits, lower 8 bits) transmission request statusf 0 1 communication end flag communication does not end after the number of bytes set in the telegraph length field have been transferred communication ends after the number of bytes set in the telegraph length field have been transferred endtrns 0 1 frame end flag the frame (transfer of the maximum number of bytes (32 bytes) prescribed by mode 1) did not end the frame (transfer of the maximum number of bytes (32 bytes) prescribed by mode 1) ended endfram 0 1 < > < > < > < > < > 401 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (a) communication error flag (ieerr)...bit 6 a flag that indicates the detection of an error during communication. 402 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user? manual u12790ej2v0ud (f) communication error triggers ? timing error occurrence conditions: occurs if the high/low level width of the communication bit has shifted from the prescribed value. remark: the respective prescribed values are set in the bit processing block and monitored by the internal 8-bit timer. an interrupt is generated when a timing error occurs. ? parity error occurrence conditions: occurs if the generated parity and the received parity in each field do not match when the iebus is a receiving unit. remark: during individual communication, an interrupt is generated if a parity error occurs in a field other than the data field. during broadcast communication, an interrupt is generated even if a parity error occurs in the data field. restriction: if there is a slave request that has lost in arbitration to a broadcast request, no interrupt is generated, even if a parity error occurs. ? nack reception occurrence conditions: this error occurs when nack is received during the ack period in each of the slave address, control, and telegraph length fields during individual communication, regardless of whether the unit is the master or a slave unit. a nack reception only occurs in individual communication. ack and nack are not discriminated in broadcast communication. remark: an interrupt is generated if nack is received in a field other than the data field. ? underrun error occurrence conditions: occurs during data transmission if there was insufficient time to write the next transmit data to the iebus data register (dr) before ack reception. remark: an interrupt is generated if an underrun occurs. ? overrun error occurrence conditions: the data interrupt request (intie1) that stores each byte of data in the iebus data register (dr) is generated, and the dr register is read by software. an overrun error occurs if this reading processing is late and its timing becomes that of the next data reception. remark: in individual communication reception, an acknowledgment is not returned in the ack period of this data, resulting in the retransmission of the data by the transmitting unit. consequently, the iebus transfer counter (ccr) is decremented, whereas the iebus communication success counter (scr) is not. in broadcast communication reception, reception is stopped by the occurrence of a communication error interrupt request (intie2), at which time the dr register is not updated. the statrx flag (bit 1 of the ssr register) also remains set (1) without generating intie1. the overrun state is released at the timing of the next data reception following the reading of dr. 403 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user? manual u12790ej2v0ud (g) overrun error - supplementary details (i) when the frame ends in the overrun state during individual communication reception if the dr register is not read after entering the overrun state and the retransmitted data reaches the maximum number of bytes (32 bytes), the frame end interrupt (intie2) is generated. the overrun state is maintained until the dr register is read after the end of the frame. (ii) if the next reception is started in the case of (i) above, or if the next reception is started without the dr register being read after the final data has been received, regardless of whether the communication is broadcast or individual even if communication to the iebus unit starts in the overrun state, the cause of the overrun, nack, is not returned in the ack period of the slave address, control, or telegraph length field (the dr register is not updated). if the next communication is not to the iebus unit, the dr register is not updated until it is read. because the iebus unit is not a communication target, the data interrupt (intie1) and communication error interrupt (intie2) are not generated. (iii) if the next transmission occurs in the overrun state the data to be transmitted next in the overrun state can be no more than 2 bytes long. because the data request interrupt (intie1) is not generated, the transmit data cannot be set, resulting in an underrun error. therefore, clear the overrun status before starting transmission. (iv) overrun state release the overrun state can only be released by reading the dr register or by a system reset. therefore, be sure to read dr in the communication error interrupt servicing program. 404 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user? manual u12790ej2v0ud (10) iebus slave status register (ssr) this register indicates the communication status of the slave unit. after receiving a slave status transmission request from the master, the cpu reads this register, and writes the slave status to the iebus data register (dr) to transmit the slave status. at this time, the telegraph length is automatically set to ?1h? so setting of the iebus telegraph length register (dlr) is not required (because it is preset by hardware). bits 6 and 7 indicate the highest mode supported by the unit, and are fixed to ?1h?(mode 1). figure 17-25. format of iebus slave status register (ssr) (a) slave transmission status flag (statslv)...bit 4 reflects the contents of the slave transmission enable flag. (b) lock status flag (statlock)...bit 2 reflects the contents of the locked flag. (c) dr reception status (statrx)...bit 1 this flag indicates the dr reception state. (d) dr transmission status (stattx)...bit 0 this flag indicates the dr transmission state. 0 slave transmission stops slave transmission enabled statslv 0 1 slave transmission status flag ssr 1 0 statslv 0 statlock statrx stattx unlock status lock status statlock 0 1 lock status flag receive data not stored in dr receive data stored in dr statrx 0 1 dr receive status transmit data not stored in dr transmit data stored in dr stattx 0 1 dr transmit status after reset: 41h r address: ffbdh < > < > < > < > 405 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (11) iebus communication success counter (scr) the iebus communication success counter (scr) indicates the number of remaining communication bytes. this register reads the count value of the counter in the value set by the iebus telegraph length register (dlr) is decremented by ack in the data field. when the count value has reached 00h , the communication end flag (endtrns) of the iebus interrupt status register (isr) is set. figure 17-26. format of iebus communication success counter (scr) note the actual hard counter consists of 9 bits. when 00h is read, it cannot be judged whether the remaining number of communication data bytes is 0 (end of communication) or 256. therefore, either the communication end flag is used, or if 00h is read when the first interrupt occurs at the beginning of communication, the remaining number of communication data bytes is judged to be 256. (12) iebus transmit counter (ccr) the iebus transmit counter (ccr) indicates the number of remaining bytes of the communication byte number specified in the communication mode. bits 7 to 0 of the iebus transmit counter (ccr) indicate the number of transfer bytes. this register reads the count value of the counter that is preset to the maximum number of transmitted bytes (32 bytes) per frame specified in mode 1. whereas scr (iebus communication success counter) is decremented during normal communication (ack), ccr is decremented when 1 byte has been communicated, regardless of whether ack or nack. when the count value has reached 00h , the frame end flag (endfram) of the iebus interrupt status register (isr) is set. the maximum number of transfer bytes of the preset value of mode 1 per frame is 20h (32 bytes). figure 17-27. format of iebus transmit counter (ccr) ccr after reset: 20h r address: ffbfh 1 byte 2 bytes : 32 bytes : 255 bytes 0 bytes (end of communication) or 256 bytes note remaining number of communication data bytes bit setting value scr 7 0 0 : 0 : 1 0 5 0 0 : 1 : 1 0 3 0 0 : 0 : 1 0 1 0 1 : 0 : 1 0 6 0 0 : 0 : 1 0 4 0 0 : 0 : 1 0 2 0 0 : 0 : 1 0 0 1 0 : 0 : 1 0 after reset: 01h r address: ffbeh 01h 02h : 20h : ffh 00h 406 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud 17.5 interrupt operations of iebus controller 17.5.1 interrupt control block the interrupt request signals are shown below. <1> communication error ieerr <2> start interrupt startf <3> status communication statusf <4> end of communication endtrns <5> end of frame endfram <6> transmit data write request stattx <7> receive data read request statrx <1> to <5> of the above interrupt requests are assigned to the iebus interrupt status register (isr). for details, refer to table 17-10 interrupt source list . the configuration of the interrupt control block is illustrated below. figure 17-28. configuration of interrupt control block caution or output of ieerr, startf, statusf, endtrns, and endfram is treated as a vectored interrupt request signal (intie2). intie1 intie2 78k/0 cpu interrupt control block iebus macro ieerr startf statusf endtrns endfram stattx statrx 407 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud 17.5.2 interrupt source list the interrupt sources are listed below. table 17-10. interrupt source list communication error interrupt source condition of generation cpu processing after remark unit field generation of interrupt timing error master/slave all fields undo communication processing communication error is or parity error reception other than data output of timing error, parity (individual) error, nack reception, underrun all fields error, and overrun error (broadcast) nack reception other than data reception (transmission) (individual) underrun error transmission data overrun error reception data (broadcast) start interrupt master slave/address slave request judgment interrupt always occurs if conflict copnflict judgment lost when master request is (if lost, remaster processing) issued. communication preparation processing slave slave/address slave request judgment generated only when slave communication preparation request is issued. processing status slave control refer to transmission processing interrupt occurs regardless of transmission example such as slave status. slave transmission enable flag. interrupt occurs if nack is returned in the control field. end of transmission data end processing by software set if scr is cleared to 0 communication reception data end processing by software receive data processing end of frame transmission data retransmission preparation processing set if ccr is cleared to 0 reception data re-reception preparation processing transmit data write transmission data transmit data write processing by set after transfer of transmission software data to internal shift register. this does not occur when the last data is transferred. receive data read reception data receive data read processing by set after normal data reception software 408 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud 17.5.3 communication error source processing list the following table shows the occurrence conditions of the communication errors (timing error, nack reception, overrun error, underrun error, and parity error), error processing by the internal iebus controller, and examples of processing by software. table 17-11. communication error source processing list (1/3) timing error occurrence unit status reception transmission condition occurrence if bit specification timing is not correct condition location of other than data field data field other than data field data field occurrence broadcast hardware ? reception stops. ? transmission stops. communication processing ? intie2 occurs ? intie2 occurs ? to start bit waiting status ? to start bit waiting status remark communication between other units does not end. software ? error processing (such as retransmission ? error processing (such as retransmission processing request) request) individual hardware ? reception stops. ? transmission stops. communication processing ? intie2 occurs. ? intie2 occurs. ? nack is returned. ? to start bit waiting status ? to start bit waiting status software ? error processing (such as retransmission ? error processing (such as retransmission processing request) request) nack reception occurrence unit status reception transmission condition occurrence unit nack transmission nack reception condition location of other than data data field other than data data field nack reception occurrence field field of data of 32nd byte broadcast hardware ????? communication processing software ????? processing individual hardware ? reception stops. ? intie2 does not ? transmission ? intie2 does ? intie2 communication processing ? intie2 occurs. occur. stops. not occur. occurs note . ? to start bit waiting ? data ? intie2 occurs. ? retrans- ? to start bit status retransmitted by ? to start bit mission waiting status other unit is waiting status processing received. software ? error processing ?? error processing ?? error processing (such as (such as processing retransmission retransmission (such as request) request) retransmission request) note both isr.6 (ieerr) and isr.2 (endfram) are set to 1. to reset them, satisfy the conditions in table 17-9. 409 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud table 17-11. communication error source processing list (2/3) overrun error underrun error occurrence unit status reception transmission condition occurrence dr cannot be read in time before the next data dr cannot be written in time before the next condition is received. data is transmitted. location of other than data field other than data field occurrence data field data field broadcast hardware ?? reception stops. ?? transmission stops. communication processing ? intie2 occurs. ? intie2 occurs. ? to start bit waiting status ? to start bit waiting status remarks 1. communication between other units does not end. 2. data cannot be received until the overrun status is cleared. software ?? dr is read and overrun status is ?? error processing (such as processing cleared. retransmission request) ? error processing (such as retransmission request) individual hardware ?? intie2 does not occur. ?? transmission stops. communication processing ? nack is returned. ? intie2 occurs. ? data is retransmitted from other ? to start bit waiting status unit. remark data cannot be received until overrun status is cleared. software ?? dr is read and overrun status is ?? error processing (such as processing cleared. retransmission request) ? error processing (such as retransmission request) 410 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud table 17-11. communication error source processing list (3/3) parity error occurrence unit status reception transmission condition occurrence received data and received parity do not match. ? condition location of other than data field data field other than data data field occurrence field broadcast hardware ? reception stops. ?? communication processing ? intie2 occurs. ? to start bit waiting status remark communication between other units does not end. software ? error processing (such as retransmission request) ?? processing individual hardware ? reception stops. ? reception does not stop. ?? communication processing ? intie2 occurs. ? intie2 does not occur. ? to start bit waiting status ? nack is returned. ? data retransmitted by other unit is received. software ? error processing (such as ??? processing retransmission request) 411 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud 17.6 interrupt generation timing and main cpu processing 17.6.1 master transmission initial preparation processing: set a unit address, slave address, control data, telegraph length, and the first byte of the transmit data. communication start processing: set the bus control register (enable communication, master request, and slave reception). figure 17-29. master transmission <1> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of slave request slave reception processing (see 17.6.1 (1) slave reception processing ) judgment of conflict result remaster request processing <2> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of end of communication end of communication processing judgment of end of frame recommunication processing (see 17.6.1 (3) recommunication processing ) remarks 1. : interrupt (intie1) occurrence (see 17.6.1 (2) interrupt (intie1) occurrence ) the transmit data of the second and subsequent bytes are written to the iebus data register (dr) by software. at this time, the data transfer direction is ram (memory) sfr (peripheral). 2. : an interrupt (intie1) does not occur. 3. n = final number of data bytes start broad- cast m address p s address p a control p a telegraph length p a data 1 pa data 1 data 2 p a data n ? 1 data n p a pa <1> <2> approx. 624 s (mode 1) approx. 390 s (mode 1) 412 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (1) slave reception processing if a slave reception request is confirmed during vectored interrupt servicing, change the data transfer direction from ram (memory) sfr (peripheral) to sfr (peripheral) ram (memory) by software until the first data is received. the maximum pending period of this data transfer direction changing processing is about 1040 s in communication mode 1. (2) interrupt (intie1) occurrence if nack is received from the slave in the data field, an interrupt (intie1) is not issued to the cpu, and the same data is retransmitted by hardware. if the transmit data is not written in time during the period of writing the next data, a communication error interrupt occurs due to occurrence of underrun, and communication ends midway. (3) recommunication processing the vectored interrupt servicing in <2> of figure 17-29 judges whether the data has been correctly transmitted within one frame. if the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the remainder of the data must be transmitted. 413 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud 17.6.2 master reception before performing master reception, it is necessary to notify the slave unit of slave transmission. therefore, more than two communication frames are necessary for master reception. the slave unit prepares the transmit data, sets (1) the slave transmission enable flag (enslvtx), and waits. initial preparation processing: set a unit address, slave address, and control data. communication start processing: set the bus control register (enable communication and master request). figure 17-30. master reception <1> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of slave request slave reception processing judgment of conflict result remaster request processing <2> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of end of communication end of communication processing judgment of end of frame frame end processing (see 17.6.2 (2) frame end processing ) remarks 1. : interrupt (intie1) occurrence (see 17.6.2 (1) interrupt (intie1) occurrence ) the receive data stored in the iebus data register (dr) is read by software. at this time, the data transfer direction is sfr (peripheral) ram (memory). 2. n = final number of data bytes approx. 1,014 s (mode 1) start broad- cast m address p s address p a control a p telegraph length a p data 1 approx. 390 s (mode 1) data 1 p a data 2 p a data n ? 1 p a data n p a <2> <1> 414 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (1) interrupt (intie1) occurrence if nack is transmitted (hardware processing) in the data field, an interrupt (intie1) is not issued to the cpu, and the same data is retransmitted from the slave. if the receive data is not read by the time the next data is received, the hardware automatically transmits nack. (2) frame end processing the vectored interrupt servicing in <2> of figure 17-30 judges whether the data has been correctly received within one frame. if the data has not been correctly received (if the number of data to be received in one frame could not be received), a request to retransmit the data must be made to the slave in the next communication frame. 415 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud 17.6.3 slave transmission initial preparation processing: set a unit address, telegraph length, and the first byte of the transmit data. communication start processing: set the bus control register (enable communication, slave transmission, and slave reception). figure 17-31. slave transmission <1> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of slave request <2> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of end of communication end of communication processing judgment of end of frame frame end processing (see 17.6.3 (2) frame end processing ) remarks 1. : interrupt (intie1) occurrence (see 17.6.3 (1) interrupt (intie1) occurrence ). the transmit data of the second and subsequent bytes are written to the iebus data register (dr) by software. at this time, the data transfer direction is ram (memory) sfr (peripheral). 2. : an interrupt (intie1) does not occur. 3. : an interrupt (intie2) occurs only when 0h, 4h, 5h, or 6h is received in the control field in the slave status (for the slave status return operation in the locked state, refer to 17.4.2 (5) iebus control data register (cdr) ). 4. n = final number of data bytes start m address p s address p a control p a data 1 pa data 1 data 2 p a data n ? 1 a data n p pa <1> <2> pa approx. 390 s (mode 1) approx. 624 s (mode 1) broad- cast telegraph length 416 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (1) interrupt (intie1) occurrence if nack is received from the master in the data field, an interrupt (intie1) is not issued to the cpu, and the same data is retransmitted by hardware. if the transmit data is not written in time during the period of writing the next data, a communication error interrupt occurs due to occurrence of underrun, and communication is abnormally ended. (2) frame end processing the vectored interrupt servicing in <2> of figure 17-31 judges whether the data has been correctly transmitted within one frame. if the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the remainder of the data must be transmitted. 417 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud 17.6.4 slave reception initial preparation processing: set a unit address. communication start processing: set the bus control register (enable communication, disable slave transmission, and enable slave reception). figure 17-32. slave reception <1> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of slave request slave processing <2> interrupt (intie2) occurrence judgment of occurrence of error error processing judgment of end of communication end of communication processing judgment of end of frame frame end processing (see 17.6.4 (2) frame end processing ) remarks 1. : interrupt (intie1) occurrence (see 17.6.4 (1) interrupt (intie1) occurrence ). the receive data stored in the iebus data register (dr) is read by software. at this time, the data transfer direction is sfr (peripheral) ram (memory). 2. n = final number of data bytes start m address p s address p a control p a data 1 pa data 1 data 2 p a data n ? 1 data n p a pa <1> pa <2> approx. 390 s (mode 1) approx. 1,014 s (mode 1) broad- cast telegraph length 418 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (1) interrupt (intie1) occurrence if nack is transmitted in the data field, an interrupt (intie1) is not issued to the cpu, and the same data is retransmitted from the master. if the receive data is not read by the time the next data is received, nack is automatically transmitted. (2) frame end processing the vectored interrupt servicing in <2> of figure 17-32 judges whether the data has been correctly received within one frame. 419 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud 17.6.5 interval of occurrence of interrupt for iebus control each control interrupt must occur at each point of communication and perform the necessary processing until the next interrupt occurs. therefore, the cpu must control the iebus control block, taking the shortest time of this interrupt into consideration. the locations at which the following error interrupts may occur are indicated by in the field where it may occur. does not mean that the interrupt occurs at each of the points indicated by . if an error interrupt (timing error, parity error, nack reception, underrun error, or overrun error) occurs, the iebus internal circuit is initialized. as a result, subsequent interrupts do not occur in that communication frame. (1) master transmission figure 17-33. master transmission (interval of interrupt occurrence) remarks 1. t: timing error a: nack reception u: underrun error : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: 6.29 mhz operation) item symbol min. unit communication starts - timing error t1 approx. 93 s communication starts - communication start interrupt t2 approx. 1,282 s communication start interrupt - timing error t3 approx. 15 s communication start interrupt - end of communication t4 approx. 1,012 s transmission data request interrupt interval t5 approx. 375 s start bit t t1 t broad- cast master address t t2 p slave address t pa at t t3 control p a a t4 tat telegraph length p a data p a communication starts communication start interrupt pa data data a p data tt t4 end of communication end of frame u u t5 a 420 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (2) master reception figure 17-34. master reception (interval of interrupt occurrence) remarks 1. t: timing error p: parity error a: nack reception : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: 6.29 mhz operation) item symbol min. unit communication starts - timing error t1 approx. 93 s communication starts - communication start interrupt t2 approx. 1,282 s communication start interrupt - timing error t3 approx. 15 s communication start interrupt - end of communication t4 approx. 1,012 s receive data read interval t5 approx. 375 s pa pa pa pa pa p a data data data p t1 t communication starts start bit broad- cast master address slave address control telegraph length data tt a end of communication end of frame communication start interrupt tt t t t at t4 t4 t5 t2 a p t a t3 421 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (3) slave transmission figure 17-35. slave transmission (interval of interrupt occurrence) remarks 1. t: timing error p: parity error a: nack reception u: underrun error : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: 6.29 mhz operation) item symbol min. unit communication starts - timing error t1 approx. 96 s communication starts - communication start interrupt t2 approx. 1,192 s communication start interrupt - timing error t3 approx. 15 s communication start interrupt - status request t4 approx. 225 s transmission data request interrupt interval t5 approx. 375 s status request - timing error t6 approx. 15 s status request - end of communication t7 approx. 787 s pa pa pa pa pa pa p t1 t tt u u tt t p p t t tt at t5 t4 t3 t6 t7 t7 t2 a p a communication starts end of communication end of frame communication start interrupt status request data data data start bit broad- cast master address slave address control data telegraph length 422 chapter 17 iebus controller ( pd178096a, 178098a, 178f098 only) user s manual u12790ej2v0ud (4) slave reception figure 17-36. slave reception (interval of interrupt occurrence) remarks 1. t: timing error p: parity error a: nack reception o: overrun error : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: 6.29 mhz operation) item symbol min. unit communication starts - timing error t1 approx. 96 s communication starts - communication start interrupt t2 approx. 1,192 s communication start interrupt - timing error t3 approx. 15 s communication start interrupt - end of communication t4 approx. 1,012 s receive data read interval t5 approx. 375 s pa pa pa pa pa p a p t1 t tt tt t p p tt at t4 t4 t5 t2 p a pt a t3 p o a p o p start bit data data data end of communication end of frame communication start interrupt communication starts broad- cast master address slave address control data telegraph length 423 user? manual u12790ej2v0ud chapter 18 interrupt functions 18.1 interrupt function types the following three types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally even if interrupts are disabled. it does not undergo interrupt priority control and is given top priority over all other interrupt requests. it generates a standby release signal. one interrupt source from the watchdog timer is incorporated as a non-maskable interrupt. (2) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high-priority interrupt group and a low-priority interrupt group by setting the priority specification flag register (pr). multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. if two or more interrupts with the same priority are generated simultaneously, each interrupt is serviced according to a predetermined priority (refer to table 18-1). a standby release signal is generated. maskable interrupts are provided in each product as follows. pd178076, 178078 internal: 13, external: 8 pd178096a, 178098a internal: 12, external: 8 pd178f098 internal: 15, external: 8 (3) software interrupt this is a vectored interrupt generated by executing the brk instruction. it is acknowledged even in an disabled interrupt state. the software interrupt does not undergo interrupt priority control. 18.2 interrupt sources and configuration the pd178076 and 178078 have a total of 22 interrupt sources, including non-maskable, maskable, and software interrupts. the pd178096a and 178098a have a total of 21 interrupt sources, and the pd178f098 has a total of 24 sources. remark either a non-maskable interrupt or a maskable interrupt (internal) can be selected as the interrupt source of the watchdog timer (intwdt). 424 chapter 18 interrupt functions user? manual u12790ej2v0ud table 18-1. interrupt sources (1/6) (1) pd178076, 178078 (1/2) default interrupt source internal/ vector basic interrupt type priority note 1 external table configuration name trigger address type note 2 non-maskable intwdt overflow of watchdog timer internal 0004h (a) (when watchdog timer mode 1 is selected) maskable 0 intwdt overflow of watchdog timer (b) (when interval timer mode is selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 0010h 7 intp6 0012h 8 intp7 0014h 9 intcsi0 end of transfer by serial interface sio0 internal 0016h (b) 10 intcsi1 end of transfer by serial interface sio1 0018h 11 intcsi3 end of transfer by serial interface sio3 001ah 12 inttm50 generation of match signal of 8-bit 001ch timer/event counter 50 13 inttm51 generation of match signal of 8-bit 001eh timer/event counter 51 14 intser0 reception error of serial interface uart0 0020h 15 intsr0 end of reception by serial interface uart0 0022h 16 intst0 end of transmission by serial interface 0024h uart0 17 intbtm0 generation of coincidence signal of basic 0026h timer btm0 18 inttm00 generation of signal indicating match 0028h between 16-bit timer counter 0 (tm0) and capture/compare register 00 (cr00) (when cr00 is used as compare register) detection of input edge of ti00/p32 pin external (d) (when cr00 is used as capture register) notes 1. if two or more maskable interrupts occur at the same time, they are acknowledged or held pending according to their default priorities. a default priority of 0 is the highest, while 22 is the lowest. 2. (a) to (e) under the heading basic configuration type correspond to (a) to (e) in figure 18-1. 425 chapter 18 interrupt functions user? manual u12790ej2v0ud table 18-1. interrupt sources (2/6) (1) pd178076, 178078 (2/2) default interrupt source internal/ vector basic interrupt type priority note 1 external table configuration name trigger address type note 2 maskable 19 inttm01 generation of signal indicating match internal 002ah (b) between 16-bit timer counter 0 (tm0) and capture/compare register 01 (cr01) (when cr01 is used as compare register) detection of input edge of ti01/p33 pin external (d) (when cr01 is used as capture register) 20 note 3 21 note 3 22 intad end of conversion by a/d converter internal 0030h (b) software brk execution of brk instruction 003eh (e) notes 1. if two or more maskable interrupts occur at the same time, they are acknowledged or held pending according to their default priorities. a default priority of 0 is the highest, while 22 is the lowest. 2. (a) to (e) under the heading basic configuration type correspond to (a) to (e) in figure 18-1. 3. there are no interrupt sources corresponding to vector addresses 002ch and 002eh. 426 chapter 18 interrupt functions user? manual u12790ej2v0ud table 18-1. interrupt sources (3/6) (2) pd178096a, 178098a (1/2) default interrupt source internal/ vector basic interrupt type priority note 1 external table configuration name trigger address type note 2 non-maskable intwdt overflow of watchdog timer internal 0004h (a) (when watchdog timer mode 1 is selected) maskable 0 intwdt overflow of watchdog timer (b) (when interval timer mode is selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 0010h 7 intp6 0012h 8 intp7 0014h 9 intcsi0 end of transfer by serial interface sio0 internal 0016h (b) 10 intcsi1 end of transfer by serial interface sio1 0018h 11 intcsi3 end of transfer by serial interface sio3 001ah 12 inttm50 generation of match signal of 8-bit 001ch timer/event counter 50 13 inttm51 generation of match signal of 8-bit 001eh timer/event counter 51 14 note 3 15 note 3 16 note 3 17 intbtm00 generation of match signal of basic internal 0026h (b) timer btm0 18 inttm00 generation of signal indicating match 0028h between 16-bit timer counter 0 (tm0) and capture/compare register 00 (cr00) (when cr00 is used as compare register) detection of input edge of ti00/p32 pin external (d) (when cr00 is used as capture register) notes 1. if two or more maskable interrupts occur at the same time, they are acknowledged or held pending according to their default priorities. a default priority of 0 is the highest, while 22 is the lowest. 2. (a) to (e) under the heading basic configuration type correspond to (a) to (e) in figure 18-1. 3. there are no interrupt sources corresponding to vector addresses 0020h, 0022h, and 0024h. 427 chapter 18 interrupt functions user? manual u12790ej2v0ud table 18-1. interrupt sources (4/6) (2) pd178096a, 178098a (2/2) default interrupt source internal/ vector basic interrupt type priority note 1 external table configuration name trigger address type note 2 maskable 19 inttm01 generation of signal indicating match internal 002ah (b) between 16-bit timer counter 0 (tm0) and capture/compare register 01 (cr01) (when cr01 is used as compare register) detection of input edge of ti01/p33 pin external (d) (when cr01 is used as capture register) 20 intie1 iebus0 data access request internal 002ch (b) 21 intie2 iebus0 communication error and start/end 002eh of communication 22 intad end of conversion by a/d converter ad1 0030h (b) software brk execution of brk instruction 003eh (e) notes 1. if two or more maskable interrupts occur at the same time, they are acknowledged or held pending according to their default priorities. a default priority of 0 is the highest, while 22 is the lowest. 2. (a) to (e) under the heading basic configuration type correspond to (a) to (e) in figure 18-1. 428 chapter 18 interrupt functions user? manual u12790ej2v0ud table 18-1. interrupt sources (5/6) (3) pd178f098 (1/2) default interrupt source internal/ vector basic interrupt type priority note 1 external table configuration name trigger address type note 2 non-maskable intwdt overflow of watchdog timer internal 0004h (a) (when watchdog timer mode 1 is selected) maskable 0 intwdt overflow of watchdog timer (b) (when interval timer mode is selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 0010h 7 intp6 0012h 8 intp7 0014h 9 intcsi0 end of transfer by serial interface sio0 internal 0016h (b) 10 intcsi1 end of transfer by serial interface sio1 0018h 11 intcsi3 end of transfer by serial interface sio3 001ah 12 inttm50 generation of match signal of 8-bit 001ch timer/event counter 50 13 inttm51 generation of match signal of 8-bit 001eh timer/event counter 51 14 intser0 reception error of serial interface uart0 0020h 15 intsr0 end of reception by serial interface uart0 0022h 16 intst0 end of transmission by serial interface uart0 0024h 17 intbtm0 generation of match signal of basic timer 0026h btm0 18 inttm00 generation of signal indicating match 0028h between 16-bit timer counter 0 (tm0) and capture/compare register 00 (cr00) (when cr00 is used as compare register) detection of input edge of ti00/p32 pin external (d) (when cr00 is used as capture register) notes 1. if two or more maskable interrupts occur at the same time, they are acknowledged or held pending according to their default priorities. a default priority of 0 is the highest, while 22 is the lowest. 2. (a) to (e) under the heading basic configuration type correspond to (a) to (e) in figure 18-1. 429 chapter 18 interrupt functions user? manual u12790ej2v0ud table 18-1. interrupt sources (6/6) (3) pd178f098 (2/2) default interrupt source internal/ vector basic interrupt type priority note 1 external table configuration name trigger address type note 2 maskable 19 inttm01 generation of signal indicating match internal 002ah (b) between 16-bit timer counter 0 (tm0) and capture/compare register 01 (cr01) (when cr01 is used as compare register) detection of input edge of ti01/p33 pin external (d) (when cr01 is used as capture register) 20 intie1 iebus0 data access request internal 002ch (b) 21 intie2 iebus0 communication error and start/end 002eh of communication 22 intad end of conversion by a/d converter ad1 0030h (b) software brk execution of brk instruction 003eh (e) notes 1. if two or more maskable interrupts occur at the same time, they are acknowledged or held pending according to their default priorities. a default priority of 0 is the highest, while 22 is the lowest. 2. (a) to (e) under the heading basic configuration type correspond to (a) to (e) in figure 18-1. 430 chapter 18 interrupt functions user? manual u12790ej2v0ud figure 18-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (c) external maskable interrupt (b) internal maskable interrupt internal bus priority controller vector table address generator standby release signal interrupt request internal bus ie pr isp mk if interrupt request priority controller vector table address generator standby release signal internal bus ie pr isp mk if priority controller vector table address generator standby release signal interrupt request edge detector external interrupt mode register (egp, egn) 431 chapter 18 interrupt functions user s manual u12790ej2v0ud figure 18-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (inttm00, inttm01) (e) software interrupt remark if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag prescaler mode register (prm0) edge detector interrupt request ie pr isp mk if priority controller vector table address generator standby release signal internal bus internal bus vector table address generator interrupt request 432 chapter 18 interrupt functions user s manual u12790ej2v0ud 18.3 interrupt function control registers the following six types of registers are used to control the interrupt functions. interrupt request flag register (if0l, if0h, if1l) interrupt mask flag register (mk0l, mk0h, mk1l) priority specification flag register (pr0l, pr0h, pr1l) external interrupt rising edge enable register (egp) external interrupt falling edge enable register (egn) program status word (psw) table 18-2 lists the interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. table 18-2. flags corresponding to interrupt request sources interrupt source interrupt request flag interrupt mask flag priority specification flag register register register intwdt wdtif if0l wdtmk mk0l wdtpr pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intp4 pif4 pmk4 ppr4 intp5 pif5 pmk5 ppr5 intp6 pif6 pmk6 ppr6 intp7 pif7 if0h pmk7 mk0h ppr7 pr0h intcsi0 csiif0 csimk0 csipr0 intcsi1 csiif1 csimk1 csipr1 intcsi3 csiif3 csimk3 csipr3 inttm50 tmif50 tmmk50 tmpr50 inttm51 tmif51 tmmk51 tmpr51 intser0 note 1 serif0 note 1 sermk0 note 1 serpr0 note 1 intsr0 note 1 srif0 note 1 srmk0 note 1 srpr0 note 1 intst0 note 1 stif0 note 1 if1l stmk0 note 1 mk1l stpr0 note 1 pr1l intbtm0 btmif0 btmmk0 btmpr0 inttm00 tmif00 tmmk00 tmpr00 inttm01 tmif01 tmmk01 tmpr01 intie1 note 2 ieif1 note 2 iemk1 note 2 iepr1 note 2 intie2 note 2 ieif2 note 2 iemk2 note 2 iepr2 note 2 intad adif admk adpr notes 1. pd178076, 178078, 178f098 only 2. pd178096a, 178098a, 178f098 only 433 chapter 18 interrupt functions user s manual u12790ej2v0ud (1) interrupt request flag registers (if0l, if0h, if1l) the interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. if0l, if0h and if1l are set by a 1-bit or 8-bit memory manipulation instruction. if if0l and if0h are used as the 16-bit register if0, use a 16-bit memory manipulation instruction for setting. reset input sets these registers to 00h. figure 18-2. format of interrupt request flag registers (if0l, if0h, if1l) id interrupt request flag 0 no interrupt request signal 1 interrupt request signal is generated; interrupt request state notes 1. these bits are provided in the pd178076, 178078, and 178f098 only. be sure to reset these bits to 0 in the pd178096a and 178098a. 2. these bits are provided in the pd178096a, 178098a, and 178f098 only. be sure to reset these bits to 0 in the pd178076 and 178078. cautions 1. the wdtif flag is r/w enabled only when the watchdog timer is used as an interval timer. if the watchdog timer is used in watchdog timer mode 1, set the wdtif flag to 0. 2. to operate the timers, serial interface, and a/d converter after the standby mode has been released, clear the interrupt request flag, because the interrupt request flag may be set by noise. pif6 srif0 note 1 0 pif5 serif0 note 1 adif pif4 tmif51 ieif2 note 2 pif3 tmif50 ieif1 note 2 pif2 csiif3 tmif01 pif1 csiif1 tmif00 pif0 csiif0 btmif0 wdtif pif7 stif0 note 1 if0l if0h if1l r/w r/w r/w r/w <0> <1> <2> <3> <4> <5> <6> <7> <0> <1> <2> <3> <4> <5> <6> <7> <0> <1> <2> <3> <4> <5> <6> 7 after reset 00h 00h 00h address ffe0h ffe1h ffe2h symbol 434 chapter 18 interrupt functions user s manual u12790ej2v0ud (2) interrupt mask flag registers (mk0l, mk0h, mk1l) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing and to set standby clear enable/disable. mk0l, mk0h and mk1l are set by a 1-bit or 8-bit memory manipulation instruction. if mk0l and mk0h are used as the 16-bit register mk0, use a 16-bit memory manipulation instruction for setting. reset input sets these registers to ffh. figure 18-3. format of interrupt mask flag registers (mk0l, mk0h, mk1l) mk control of interrupt servicing 0 interrupt servicing enabled 1 interrupt servicing disabled notes 1. these bits are provided in the pd178076, 178078, and 178f098 only. be sure to reset these bits to 0 in the pd178096a and 178098a. 2. these bits are provided in the pd178096a, 178098a, and 178f098 only. be sure to reset these bits to 0 in the pd178076 and 178078. cautions 1. if the wdtmk flag is read when the watchdog timer is used in watchdog timer mode 1, the mk0 value becomes undefined. 2. because port 0 has an alternate function as an external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode. pmk6 srmk0 note 1 1 pmk5 sermk0 note 1 admk pmk4 tmmk51 iemk2 note 2 pmk3 tmmk50 iemk1 note 2 pmk2 csimk3 tmmk01 pmk1 csimk1 tmmk00 pmk0 csimk0 btmmk0 wdtmk pmk7 stmk0 note 1 mk0l mk0h mk1l r/w r/w r/w r/w ffe4h ffe5h ffe6h ffh ffh ffh <0> <1> <2> <3> <4> <5> <6> <7> <0> <1> <2> <3> <4> <5> <6> <7> <0> <1> <2> <3> <4> <5> <6> 7 after reset address symbol 435 chapter 18 interrupt functions user s manual u12790ej2v0ud (3) priority specification flag registers (pr0l, pr0h, pr1l) the priority specification flags are used to set the corresponding maskable interrupt priority order. pr0l, pr0h and pr1l are set by a 1-bit or 8-bit memory manipulation instruction. if pr0l and pr0h are used as the 16-bit register pr0, use a 16-bit memory manipulation instruction for setting. reset input sets these registers to ffh. figure 18-4. format of priority specification flag registes (pr0l, pr0h, pr1l) pr priority level selection 0 high priority level 1 low priority level notes 1. these bits are provided in the pd178076, 178078, and 178f098 only. be sure to set these bits to 1 in the pd178096a and 178098a. 2. these bits are provided in the pd178096a, 178098a, and 178f098 only. be sure to set these bits to 1 in the pd178076 and 178078. caution when the watchdog timer is used in watchdog timer mode 1, set the wdtpr flag to 1. ppr6 srpr0 note 1 1 ppr5 serpr0 note 1 adpr ppr4 tmpr51 iepr2 note 2 ppr3 tmpr50 iepr1 note 2 ppr2 csipr3 tmpr01 ppr1 csipr1 tmpr00 ppr0 csipr0 btmpr0 wdtpr ppr7 stpr0 note 1 pr0l pr0h pr1l r/w r/w r/w r/w <0> <1> <2> <3> <4> <5> <6> <7> <0> <1> <2> <3> <4> <5> <6> <7> <0> <1> <2> <3> <4> <5> <6> 7 fff8h ffe9h ffeah ffh ffh ffh after reset address symbol 436 chapter 18 interrupt functions user s manual u12790ej2v0ud (4) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) these registers set the valid edge for intp0 to intp7. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to 00h. figure 18-5. format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) egpn egnn selection of intpn pin valid edge (n = 0 to 7) 0 0 interrupts disabled 0 1 falling edge 1 0 rising edge 1 1 both falling and rising edges 7 egp7 7 egn7 6 egp6 6 egn6 5 egp5 5 egn5 4 egp4 4 egn4 3 egp3 3 egn3 2 egp2 2 egn2 1 egp1 1 egn1 0 egp0 0 egn0 egp egn r/w r/w r/w after reset 00h 00h address ff48h ff49h symbol 437 chapter 18 interrupt functions user s manual u12790ej2v0ud (5) program status word (psw) the program status word is a register used to hold the instruction execution result and the current status of an interrupt request. the ie flag to set maskable interrupt enable/disable and the isp flag to control nesting interrupt are mapped in the psw. besides 8-bit unit read/write, this register can carry out operations via bit manipulation instructions and dedicated instructions (ei and di). when a vectored interrupt request is acknowledged, if the brk instruction is executed, the contents of the psw are automatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the isp flag. the acknowledged interrupt is also saved into the stack by the push psw instruction and restored from the stack by the reti, retb, and pop psw instructions. reset input sets the psw to 02h. figure 18-6. configuration of program status word 7 ie psw 6 z 5 rbs1 4 ac 3 rbs0 2 0 1 isp 0 cy 02h after reset isp 0 used when normal instruction is executed priority of interrupt currently being serviced high-priority interrupt being serviced (low-priority interrupts disabled) 1 interrupt request not acknowledged or low-priority interrupt being serviced (all-maskable interrupts enabled) ie enable/disable of interrupt request acknowledgment 0 disabled 1 enabled 438 chapter 18 interrupt functions user s manual u12790ej2v0ud 18.4 interrupt servicing operations 18.4.1 non-maskable interrupt request acknowledgment operation a non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledgment disabled state. it does not undergo interrupt priority control and has the highest priority of all interrupts. if a non-maskable interrupt request is acknowledged, the acknowledged interrupt is saved in the stack, the program status word (psw), and the program counter (pc), in that order, the ie and isp flags are reset to 0, and the vector table contents are loaded into the pc and branched. a new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after execution of the current non-maskable interrupt servicing program has finished (following reti instruction execution) and one main routine instruction is executed. if a new non-maskable interrupt request is generated twice or more during non-maskable interrupt servicing program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt servicing program execution. figure 18-7 shows the flowchart from generation of a non-maskable interrupt request to acknowledgment. figure 18-8 shows the timing of acknowledging the non-maskable interrupt request, and figure 18-9 shows the operation performed if a more than one non-maskable interrupt request occurs. 439 chapter 18 interrupt functions user s manual u12790ej2v0ud figure 18-7. flowchart from generation of non-maskable interrupt request to acknowledgment wdtm: watchdog timer mode register wdt: watchdog timer figure 18-8. non-maskable interrupt request acknowledgment timing wdtm4=1 (with watchdog timer mode selected)? overflow in wdt? wdtm3=0 (with non-maskable interrupt request selected)? interrupt request generation wdt interrupt servicing? interrupt control register unaccessed? interrupt servicing start interrupt request held pending reset processing interval timer start no yes yes no yes no yes no yes no instruction instruction cpu instruction wdtif psw and pc saved jump to interrupt servicing interrupt servicing program 440 chapter 18 interrupt functions user s manual u12790ej2v0ud figure 18-9. non-maskable interrupt request acknowledgment operation (a) if a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution (b) if two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution main routine nmi request execution of one instruction nmi request nmi request is held pending. pending nmi request is serviced. nmi request nmi request held pending. only one nmi request is acknowledged even if two or more nmi requests are generated. nmi request held pending. main routine execution of one instruction 441 chapter 18 interrupt functions user s manual u12790ej2v0ud 18.4.2 maskable interrupt request acknowledgment operation a maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask (mk) flag of the interrupt request is cleared to 0. a vectored interrupt request is acknowledged in an interrupt enabled state (with the ie flag set to 1). however, a low-priority interrupt request is not acknowledged during high-priority interrupt servicing (with the isp flag reset to 0). the wait times from maskable interrupt request generation to interrupt request servicing are as follows. for the interrupt acknowledgment timing, refer to figures 18-11 and 18-12. table 18-3. times from maskable interrupt request generation to interrupt servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a divide instruction, the wait time is maximized. remark 1 clock : (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request specified as having a priority by the priority specification flag is acknowledged first. if two or more requests are specified as having the same priority by the priority specification flag, the default priorities apply. any pending interrupt requests are acknowledged when they become acknowledgeable. figure 18-10 shows the interrupt request acknowledgment algorithms. if a maskable interrupt request is acknowledged, the acknowledged interrupt request is saved in the stack, the program status word (psw), and the program counter (pc), in that order, the ie flag is reset to 0, and the acknowledged interrupt priority specification flag contents are transferred to the isp flag. further, the vector table data determined for each interrupt request is loaded into the pc and branched. return from the interrupt is possible using the reti instruction. f cpu 1 442 chapter 18 interrupt functions user s manual u12790ej2v0ud figure 18-10. interrupt request acknowledgment processing algorithm if: interrupt request flag mk: interrupt mask flag pr: priority specification flag ie: flag controlling acknowledgment of maskable interrupt request (1 = enabled, 0 = disabled) isp: flag indicating priority of interrupt currently being serviced (0 = interrupt with high priority being serviced, 1 = interrupt request is not acknowledged, or interrupt with low priority is being serviced) start if = 1? mk = 0? pr = 0? any simultaneously generated pr=0 interrupt requests? any simultaneously generated high-priority interrupt requests ? ie = 1? isp = 1? vectored interrupt servicing interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending vectored interrupt servicing any high- priority interrupt request among simultaneously generated pr=0 interrupts? ie = 1? yes (high priority) yes no yes no no no yes (interrupt request generation) no yes no (low priority) yes yes no yes yes no no 443 chapter 18 interrupt functions user s manual u12790ej2v0ud figure 18-11. interrupt request acknowledgment timing (minimum time) 1 f cpu remark 1 clock: (f cpu : cpu clock) figure 18-12. interrupt request acknowledgment timing (maximum time) 1 f cpu remark 1 clock: (f cpu : cpu clock) instruction instruction psw and pc saved jump to interrupt servicing 6 clocks interrupt servicing program 8 clocks 7 clocks cpu processing if ( pr = 1) if ( pr = 0) instruction divide instruction psw and pc saved jump to interrupt servicing 6 clocks interrupt servicing program 33 clocks 32 clocks cpu processing if ( pr = 1) if ( pr = 0) 25 clocks 444 chapter 18 interrupt functions user s manual u12790ej2v0ud 18.4.3 software interrupt request acknowledgment operation a software interrupt request is acknowledged by brk instruction execution. software interrupts cannot be disabled. if a software interrupt request is acknowledged, it is saved in the stack, the program status word (psw), and the program counter (pc), in that order, the ie flag is reset to 0, and the contents of the vector tables (003eh and 003fh) are loaded into the pc and branched. return from a software interrupt is possible using the retb instruction. caution do not use the reti instruction for returning from a software interrupt. 445 chapter 18 interrupt functions user s manual u12790ej2v0ud 18.4.4 multiple servicing interrupt acknowledgment of an interrupt request while another interrupt is being serviced is called multiple interrupt servicing. multiple interrupt servicing does not take place unless interrupts (except the non-maskable interrupt) are enabled to be acknowledged (ie = 1). acknowledgment of another interrupt request is disabled (ie = 0) when one interrupt has been acknowledged. therefore, to enable multiple interrupt servicing, the ei flag must be set to 1 during interrupt servicing, to enable other interrupts. multiple interrupt servicing may not occur even when interrupts are enabled. this is controlled by the priorities of the interrupts. although two types of priorities, default priority and programmable priority, may be assigned to an interrupt, multiple interrupt servicing is controlled by using the programmable priority. if an interrupt with the same priority level as or a higher priority than the interrupt currently being serviced occurs, that interrupt can be acknowledged and serviced. if an interrupt with a priority lower than that of the interrupt currently being serviced occurs, that interrupt cannot be acknowledged and serviced. an interrupt that is not acknowledged and serviced because it is disabled or it has a low priority is held pending. this interrupt is acknowledged after servicing of the current interrupt has been completed and one instruction of the main routine has been executed. multiple interrupt servicing is not enabled while the non-maskable interrupt is being serviced. table 18-4 shows the interrupts to which multiple interrupt servicing can be applied, and figure 18-13 shows an example of multiple interrupt servicing. table 18-4. interrupt requests enabled for multiple interrupt servicing maskable interrupt request pr = 0 pr = 1 ie = 1 ie = 0 ie = 1 ie = 0 non-maskable interrupt d d d d d isp = 0 e e d d d isp = 1 e e d e d software interrupt servicing e e d e d remarks 1. e: multiple interrupt servicing enabled 2. d: multiple interrupt servicing disabled 3. isp and ie are the flags contained in the psw isp = 0: an interrupt with higher priority is being serviced isp = 1: an interrupt request is not acknowledged or an interrupt with lower priority is being serviced ie = 0: interrupt request acknowledgment is disabled ie = 1: interrupt request acknowledgment is enabled 4. pr is a flag contained in pr0l and pr0r. pr = 0: higher priority level pr = 1: lower priority level interrupt being serviced non-maskable interrupt request interrupt request maskable interrupt 446 chapter 18 interrupt functions user s manual u12790ej2v0ud figure 18-13. example of multiple interrupt servicing (1/2) example 1. example where multiple interrupt servicing takes place two times example 2. example where multiple interrupt servicing does not take place because of priority control two interrupt requests, intyy and intzz, are acknowledged while interrupt intxx is being serviced, and multiple interrupt servicing takes place. before each interrupt request is acknowledged, the ei instruction is always executed, and interrupts are enabled. interrupt request intyy that is generated while interrupt intxx is being serviced is not acknowledged because its priority is lower than that of intxx, and therefore, multiple interrupt servicing does not take place. the intyy request is held pending, and is acknowledged after one instruction of the main routine has been executed. pr = 0: high-priority level pr = 1: low-priority level ie = 0: acknowledging interrupt requests is disabled. main processing ei intxx (pr = 1) intyy (pr = 0) ie = 0 ei reti intxx servicing intzz (pr = 0) ie = 0 ei reti intyy servicing ie = 0 reti intzz servicing main processing intxx servicing intyy servicing intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 1) ei ie = 0 ei reti reti 447 chapter 18 interrupt functions user s manual u12790ej2v0ud figure 18-13. example of multiple interrupt servicing (2/2) example 3. example where multiple interrupt servicing does not take place because interrupts are not enabled because interrupts are not enabled (ei instruction is not issued) in the servicing of interrupt intxx, interrupt request intyy is not acknowledged, and multiple interrupt servicing does not take place. the intyy request is held pending, and is acknowledged after one instruction of the main routine has been executed. pr = 0: high priority level ie = 0: acknowledging interrupts is disabled. main processing intxx servicing intyy servicing intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 0) ie = 0 reti reti ei 448 chapter 18 interrupt functions user s manual u12790ej2v0ud 18.4.5 pending interrupt requests even if an interrupt request is generated, the following instructions hold it pending. mov psw, #byte mov a, psw mov psw, a mov1 psw.bit, cy mov1/and1/or1/xor1 cy, psw.bit set1/clr1 psw.bit retb reti push psw pop psw bt/bf/btclr psw.bit, $addr16 ei di instructions manipulating if0l, if0h, if1l, mk0l, mk0h, mk1l, pr0l, pr0h, pr1l, egp, and egn registers caution because the ie flag is cleared to 0 by the software interrupt (caused by execution of the brk instruction), a maskable interrupt request is not acknowledged even if it occurs while the brk instruction is being executed. however, the non-maskable interrupt is acknowledged. figure 18-14. pending interrupt requests remarks 1. instruction n: instruction that holds interrupt request pending 2. instruction m: instruction that does not hold interrupt request pending 3. operation of if is not affected by value of pr. cpu processing if instruction n instruction m psw and pc saved jump to interrupt servicing interrupt servicing program 449 user? manual u12790ej2v0ud chapter 19 pll frequency synthesizer 19.1 function of pll frequency synthesizer the pll (phase locked loop) frequency synthesizer is used to lock the frequency in the mf (middle frequency), hf (high frequency), and vhf (very high frequency) ranges to a specific frequency by means of phase difference comparison. the pll frequency synthesizer divides the frequency of the signal input from the vcol or vcoh pin by using a programmable divider, and outputs the phase difference between the frequency of this signal and the reference frequency from the eo0 and eo1 pins. the following two types of input pins and five frequency division modes are used. (1) direct division (mf) mode the vcol pin is used. the vcoh pin is set in the status specified by bit 3 (vcohdmd) of the pll mode select register (pllmd). (2) pulse swallow (hf) mode the vcol pin is used. the vcoh pin is set in the status specified by bit 3 (vcohdmd) of pllmd. (3) pulse swallow (vhf) mode the vcoh pin is used. the vcol pin is set in the status specified by bit 2 (vcoldmd) of pllmd. (4) vcol and vcoh pin disable the vcol and vcoh pins are set in the status specified by bits 2 (vcoldmd) and 3 (vcohdmd) of pllmd. at this time, the phase comparator, reference frequency generator, and charge pump operate. (5) pll disable the pll disabled status is set by the pll reference mode register (pllrf). the vcoh and vcol pins are set in the status specified by bits 2 (vcoldmd) and 3 (vcohdmd) of pllmd. the eo0 and eo1 pins go into a high-impedance state. at this time, all the internal pll operations are stopped. these division modes are selected by using the pll mode select register (pllmd). the division value (n value) is set to the programmable divider by using the pll data register. frequency division in each of the above modes is carried out according to the value (n value) set to the programmable divider. table 19-1 shows the division modes, input pins used (vcol pin or vcoh pin), and the value that can be set to the programmable divider. 450 chapter 19 pll frequency synthesizer user? manual u12790ej2v0ud table 19-1. division mode, input pin, and division value division mode pin used value that can be set direct division (mf) vcol 32 to 2 12 ?1 pulse swallow (hf) vcol 1024 to 2 17 ?1 pulse swallow (vhf) vcoh 1024 to 2 17 ?1 caution for the frequencies that can actually be input, and the input amplitude, refer to chapter 25 electrical specifications. 451 chapter 19 pll frequency synthesizer user? manual u12790ej2v0ud 19.2 configuration of pll frequency synthesizer the pll frequency synthesizer consists of the following hardware. table 19-2. configuration of pll frequency synthesizer item configuration data registers pll data register l (pllrl) pll data register h (pllrh) pll data register 0 (pllr0) control registers pll mode select register (pllmd) pll reference mode register (pllrf) pll unlock ff judge register (pllul) pll data transfer register (pllns) figure 19-1. block diagram of pll frequency synthesizer note external circuit internal bus internal bus pll mode select register pwm data transfer register pll ns0 pll md0 pll md1 pll rf2 pll rf1 pll rf0 pll ul0 eoc on0 eo select register pll reference mode register pll unlock ff judge register pll rf3 2 input select block programmable divider phase comparator ( -det) unlock ff reference frequency generator 0.3 mhz or 4.5 mhz 4 charge pump eo1 eo0 vcoh vcol mixer 2 f n f r pll data register (pllrl, pllrh, pllr0) voltage control generator lowpass filter note note eoc on1 vcol dmd vcoh dmd 452 chapter 19 pll frequency synthesizer user s manual u12790ej2v0ud (1) pll data register l (pllrl), pll data register h (pllrh), and pll data register 0 (pllr0) these registers set the division value of the pll frequency synthesizer. the division value of the pll frequency synthesizer is made up of 17 bits. the higher 16 bits of this value are set by pll data register l (pllrl) and pll data register h (pllrh). the higher 16 bits can also be set by the pll data register (pllr). the least significant bit is set by bit 7 (pllscn) of pll data register 0 (pllr0). the contents of these registers are undefined after reset. these registers hold the current values in the stop and halt modes. (2) input select block the input select block consists of the vcol and vcoh pins, and input amplifiers of the respective pins. (3) programmable divider the programmable divider consists of two modulus prescalers, a programmable counter (12 bits), a swallow counter (5 bits), and a division mode select switch. (4) reference frequency generator the reference frequency generator consists of a divider that generates the reference frequency f r of the pll frequency synthesizer, and a multiplexer. (5) phase comparator the phase comparator ( -det) compares the phase of the divided frequency output f n of the programmable divider with that of the reference frequency output f r of the reference frequency generator, and outputs an up request signal (up) and down request signal (dw). (6) unlock ff the unlock ff detects the unlock status of the pll frequency synthesizer from the up request signal (up) and down request signal (dw) of the phase comparator ( -det). (7) charge pump the charge pump outputs the result of the output of the phase comparator from the error out pins (eo0 and eo1 pins). 453 chapter 19 pll frequency synthesizer user s manual u12790ej2v0ud 19.3 registers controlling pll frequency synthesizer the pll frequency synthesizer is controlled by the following four registers. pll mode select register (pllmd) pll reference mode register (pllrf) pll unlock ff judge register (pllul) pll data transfer register (pllns) (1) pll mode select register (pllmd) this register selects the input pin and division mode of the pll frequency synthesizer. pllmd is set by a 1-bit or 8-bit memory manipulation instruction. the value of this register is set to 00h after reset. in the stop mode, only bits 3 and 2 (vcohdmd and vcoldmd) retain the previous value. bits 1 and 0 (pllmd1 and pllmd0) are reset to 0. in the halt mode, this register holds the value immediately before the halt mode was set. figure 19-2. format of pll mode select register (pllmd) vcoh selection of disable status of vcoh pin dmd 0 connected to pull-down resistor. 1 high-impedance status vcol selection of disable status of vcol pin dmd 0 connected to pull-down resistor. 1 high-impedance status pllmd1 pllmd0 selection of division mode of pll frequency synthesizer and vco input pin 0 0 vcol and vcoh pins disabled note 0 1 direct division (vcol pin and mf mode) 1 0 pulse swallow (vcoh pin and vhf mode) 1 1 pulse swallow (vcol pin and hf mode) note this does not mean that the pll is disabled. the vcoh and vcol pins become the status specified by bit 3 (vcohdmd) and bit 2 (vcoldmd). the eo0 and eo1 pins go low. remark bits 4 to 7 are fixed to 0 by hardware. 7 0 6 0 5 0 4 0 <3> vcohdmd <2> vcoldmd pllmd1 pllmd0 symbol pllmd r/w r/w after reset 00h address ffa0h <1> <0> 454 chapter 19 pll frequency synthesizer user s manual u12790ej2v0ud (2) pll reference mode register (pllrf) this register selects the reference frequency f r of the pll frequency synthesizer and sets the disabled status of the pll frequency synthesizer. pllrf is set by 1-bit or 8-bit memory manipulation instruction. the value of this register is set to 0fh after reset and in the stop mode. in the halt mode, this register holds the value immediately before the halt mode was set. figure 19-3. format of pll reference mode register (pllrf) pllrf3 pllrf2 pllrf1 pllrf0 settings of reference frequency f r of pll frequency synthesizer 000050 khz 000125 khz 0010 12.5 khz 00119 khz 01001 khz 01013 khz 011010 khz 0111 setting prohibited 1 pll disable note note when pll disable is selected, the status of the vcol, vcoh, eo0, and eo1 pins are as follows. vcoh, vcol pins: status specified by bit 3 (vcohdmd) and bit 2 (vcoldmd) of the pll mode select register (pllmd). eo0, eo1 pins: high-impedance state remark bits 4 to 7 are fixed to 0 by hardware. : don t care 7 0 6 0 5 0 4 0 pllrf3 pllrf2 pllrf1 pllrf0 symbol pllrf r/w r/w address ffa1h after reset 0fh <1> <0> <3> <2> 455 chapter 19 pll frequency synthesizer user? manual u12790ej2v0ud (3) pll unlock ff judge register (pllul) this register detects whether the pll frequency synthesizer is in the unlock status. because this register is an r&reset register, it is reset to 0 after it has been read. the value of this register is set to 0 h note 1 after reset. in the stop and halt modes, this register holds the value immediately before the stop or halt mode was set. figure 19-4. format of pll unlock ff judge register (pllul) pllul0 detection of status of unlock ff 0 unlock ff = 0: pll lock status 1 unlock ff = 1: pll unlock status notes 1. the value of bit 0 (pllul0) after reset differs depending on the type of reset that has been executed (refer to the table below). 2. bit 0 (pllul0) is r&reset. 76543210 after power-on clear 0000000 undefined reset watchdog timer held reset input held stop mode held halt mode held remark bits 1 to 7 are fixed to 0 by hardware. 7 0 6 0 5 0 4 0 3 0 2 0 1 0 pllul0 symbol pllul r/w r note 2 after reset 0 h note 1 address ffa2h <0> 456 chapter 19 pll frequency synthesizer user s manual u12790ej2v0ud (4) pll data transfer register (pllns) this register transfers the values of the pll data registers (pllrl, pllrh, and pllr0) to the programmable counter and swallow counter. the value of this register is 00h after reset and in the stop mode. in the halt mode, this register holds the previous value immediately before the halt mode was set. figure 19-5. format of pll data transfer register (pllns) pllns0 transfer of value of pll data register to programmable counter and swallow counter 0 not transferred 1 transferred remark bits 1 to 7 are fixed to 0 by hardware. 7 0 6 0 5 0 4 0 3 0 2 0 1 0 pllns0 symbol pllns r/w w after reset 00h address ffa3h <0> 457 chapter 19 pll frequency synthesizer user s manual u12790ej2v0ud 19.4 operation of pll frequency synthesizer 19.4.1 operation of each block of pll frequency synthesizer (1) operation of input select block and programmable divider the input select block and programmable divider select the input pin and division mode of the pll frequency synthesizer and divide the frequency in the selected division mode, according to the setting of the pll mode select register (pllmd). the programmable counter (12 bits) and pulse swallow counter (5 bits) are binary counters. the division value (n value) is set to the programmable counter and swallow counter by the pll data registers (pllrl, pllrh, and pllr0). when the n value has been transferred to the programmable counter and swallow counter, frequency division is performed in the selected division mode according to the status of bit 0 (pllns0) of the pll data transfer register. figure 19-6 shows the configuration of the input select block and programmable divider. figure 19-6. configuration of input select block and programmable divider (2) operation of reference frequency generator the reference frequency generator divides the 6.3 mhz or 4.5 mhz output of the crystal resonator and generates seven types of reference frequency f r for the pll frequency synthesizer. reference frequency f r is selected by the pll reference mode register (pllrf). figure 19-7 shows the configuration of the reference frequency generator. pll ns0 vcoh vhf amp amp hf mf vhf hf mf 12 bits internal bus pll data registers (pllrl, pllrh, pllr0) 5 bits f n two modulus prescalers (1/32, 1/33) programmable counter (12 bits) swallow counter (5 bits) vcol to -det pwm data transfer register vcoh dmd vcol dmd 458 chapter 19 pll frequency synthesizer user s manual u12790ej2v0ud figure 19-7. reference frequency generator configuration (3) operation of phase comparator ( -det) figure 19-8 shows the configuration of the phase comparator ( -det), charge pump, and unlock ff. the phase comparator ( -det) compares the phase of the divided frequency f n of the programmable divider with that of the reference frequency f r of the reference frequency generator, and outputs an up request signal, up, or a down request signal, dw. if the divided frequency f n is lower than the reference frequency f r , the up request signal is output. if f n is higher than f r , the down request signal is output. figure 19-9 shows the relationships between the reference frequency f r , divided frequency f n , up request signal up, and down request signal dw. when the pll is disabled, neither the up nor the down request signal is output. the up and down request signals are input to the charge pump and unlock ff. figure 19-8. phase comparator, charge pump, and unlock ff configuration pllrf3 to pllrf0 4-16 decoder divider 6.3 mhz or 4.5 mhz mux 1 khz 3 khz 9 khz 25 khz 50 khz pll disable signal f r to -det f n eo1 pllul unlock ff charge pump eo0 pll disable signal f r up reference frequency generator programmable divider dw phase comparator ( -det) 459 chapter 19 pll frequency synthesizer user s manual u12790ej2v0ud figure 19-9. relationship between f r , f n , up, and dw (a) if f n advances f r in phase (4) operation of charge pump the charge pump outputs the result of the up request (up) or down request (dw) signal from the phase comparator ( -det) from the error out pins (eo0 and eo1 pins). table 19-3 shows the output signals. the eo0 and eo1 pins are voltage-driven type pins. figure 19-10 shows the configuration of the error out pins. (d) if f n is lower than f r (c) if f n and f r are in phase (b) if f n advances f r in phase f r f n up dw f r f n up dw f r f n up dw f r f n up dw 460 chapter 19 pll frequency synthesizer user s manual u12790ej2v0ud table 19-3. error out output signal relationship between divided frequency error out output signal f n and reference frequency f r when f r > f n low level when f r < f n high level when f r = f n floating (high impedance) figure 19-10. error out pin configuration p-ch eo1 gndpll v dd pll v dd pll n-ch dw up gndpll p-ch eo0 n-ch 461 chapter 19 pll frequency synthesizer user s manual u12790ej2v0ud (5) operation of unlock ff the unlock ff detects the unlock status of the pll frequency synthesizer. it detects the unlock status of the pll frequency synthesizer from the up request signal up and down request signal dw of the phase comparator ( -det). because either of the up request or down request signal outputs a low level in the unlock status, the unlock status can be detected by using this low-level signal. the status of the unlock ff is detected by bit 0 (pllul0) of the pll unlock ff judge register (pllul). the unlock ff is set at the cycle of the reference frequency f r selected at that time. the pll unlock ff judge register is reset when its contents have been read. to read the pll unlock ff judge register, therefore, it must be read at a cycle longer than the cycle (1/f r ) of the reference frequency. 19.4.2 operation to set n value of pll frequency synthesizer the division value (n value) is set to the programmable counter (12 bits) and swallow counter (5 bits) by the pll data registers (pllrl, pllrh, and pllr0). when the n value has been transferred to the programmable counter and swallow counter by bit 0 (pllns0) of the pll data transfer register (pllns), frequency division is carried out in the selected division mode. examples of setting the n value in the respective division modes (mf, hf, and vhf) are shown below. (1) direct division mode (mf) (a) calculating division value n (value set to pll data register) n = f vcol f r where, f vcol : input frequency of v col pin f r : reference frequency (b) example of setting pll data register an example of setting the pll data register to receive broadcast stations in the following mw band is shown below. receive frequency: 1422 khz (mw band) reference frequency: 9 khz intermediate frequency: 450 khz division value n is calculated as follows: n = f vcol = 1422 + 450 = 208 (decimal) f r 9 = 0d0h (hexadecimal) 462 chapter 19 pll frequency synthesizer user s manual u12790ej2v0ud data is set to the pll data registers (pllr and pllr0) as follows. after setting the above pll data registers (pllr and pllr0), data must be transferred to the programmable counter by setting bit 0 (pllns0) of the pll data transfer register (pllns). (2) pulse swallow mode (hf) (a) calculating division value n (value set to pll data register) n = f vcol f r where, f vcol : input frequency of v col pin f r : reference frequency (b) example of setting pll data register an example of setting the pll data register to receive broadcast stations in the following sw band is shown below. receive frequency: 25.50 mhz (sw band) reference frequency: 10 khz intermediate frequency: 450 khz division value n is calculated as follows: n = f vcol = 25500 + 450 = 2595 (decimal) f r 10 = 0a23h (hexadecimal) pllr programmable counter value don' t care fixed to 0 pllrl pllrh b7 b16 b6 b15 b5 b14 b4 b13 b3 b12 b2 b11 b1 b10 b0 b9 b7 b8 b6 b7 b5 b6 b4 b5 000 0d0 011010000 b3 b4 b2 b3 b1 b2 b0 b1 b7 b0 b6 b5 b4 b3 b2 b1 b0 pllr0 pllscn 463 chapter 19 pll frequency synthesizer user s manual u12790ej2v0ud because the least significant bit of division value n must be set to bit 7 (pllscn) of pll data register 0 (pllr0), data must be set by shifting the result of the above calculation 1 bit to the right. data is set to the pll data registers (pllr and pllr0) as follows. after setting the above pll data registers (pllr and pllr0), data must be transferred to the programmable counter and swallow counter by setting bit 0 (pllns0) of the pll data transfer register (pllns). in this example, a value of half the n value is set to the higher 16 bits of the pll data register (pllr) by shifting the n value resulting from calculation 1 bit to the right. if the n value is calculated as follows with the least significant bit of the n value in pllscn fixed to 0, the result of the calculation (n pllr ) can be set to the pll data register (pllr) as is. if the calculation result is set in this way, however, the input frequency (f vcol ) is 2 f r (reference frequency) of the set value n pllr . n pllr = f vcol 2f r pllr programmable counter value fixed to 0 pllrl pllrh b7 b16 b6 b15 b5 b14 b4 b13 b3 b12 b2 b11 b1 b10 b0 b9 b7 b8 b6 b7 b5 b6 b4 b5 000 05110 0511h 00101 00010 0001 b3 b4 b2 b3 b1 b2 b0 b1 b7 b0 b6 b5 b4 b3 b2 b1 b0 pllr0 pllscn value shifted 1 bit to right 000001010001 0001 0 0 shifted 1 bit to right a23h result of calculation (n value) 000010100010 0011 swallow counter value 464 chapter 19 pll frequency synthesizer user s manual u12790ej2v0ud (3) pulse swallow mode (vhf) (a) calculating division value n (value set to pll data register) n = f vcoh f r where, f vcoh : input frequency of vcoh pin f r : reference frequency (b) example of setting pll data register an example of setting the pll data register to receive broadcast stations in the following fm band is shown below. receive frequency: 100.0 mhz (fm band) reference frequency: 50 khz intermediate frequency: +10.7 mhz division value n is calculated as follows. n = f vcoh = 100.0 + 10.7 = 2214 (decimal) f r 0.05 = 08a6h (hexadecimal) because the least significant bit of division value n must be set to pll data register 0 (pllr0), data must be set by shifting the value calculated by the above expression 1 bit to the right. data is set to the pll data registers (pllr and pllr0) as follows. pllr pllrl pllrh b7 b16 b6 b15 b5 b14 b4 b13 b3 b12 b2 b11 b1 b10 b0 b9 b7 b8 b6 b7 b5 b6 b4 b5 000 04530 0453h 00100 00110 0101 b3 b4 b2 b3 b1 b2 b0 b1 b7 b0 b6 b5 b4 b3 b2 b1 b0 pllr0 pllscn value shifted 1 bit to right 000001000101 0011 0 0 shifted 1 bit to right 8a6h result of calculation (n value) 000010001010 0110 programmable counter value fixed to 0 swallow counter value 465 chapter 19 pll frequency synthesizer user s manual u12790ej2v0ud after setting the above pll data registers (pllr and pllr0), data must be transferred to the programmable counter and swallow counter by setting bit 0 (pllns0) of the pll data transfer register (pllns). in this example, a value of half the n value is set to the higher 16 bits of the pll data register (pllr) by shifting the n value resulting from calculation 1 bit to the right. if the n value is calculated as follows with the least significant bit of the n value in pllscn fixed to 0, the result of the calculation (n pllr ) can be set to the pll data register (pllr) as is. if the calculation result is set in this way, however, the input frequency (f vcoh ) is 2 f r (reference frequency) of the set value n pllr . n pllr = f vcoh 2f r 466 chapter 19 pll frequency synthesizer user s manual u12790ej2v0ud 19.5 pll disable status the pll frequency synthesizer can be stopped (pll disable status) by performing any of the following settings while the pll frequency synthesizer is operating. setting the value of bit 3 (pllrf3) of the pll reference mode register (pllrf) to 1 to set the pll disable status setting stop mode using the stop instruction setting the reset using the reset function the following table shows the operation of each block and the status of each register in the pll disable status. table 19-4. operation of each block and register status in pll disable status block/register status in pll disable status vcol and vcoh pins status set in bit 3 (vcohdmd) and bit 2 (vcoldmd) of pllmd programmable divider division stops reference frequency generator output stops phase comparator output stops eo0 and eo1 pin high impedance pll mode select register retains value on execution of write instruction pll data register pll unlock ff judge register 19.6 notes on pll frequency synthesizer notes on using pll frequency synthesizer because the input pins (vcol and vcoh pins) of the pll frequency synthesizer are provided with an ac amplifier, cut the dc component of the input signal by connecting a capacitor to the input pins in series. the potential of the selected input pin is intermediate (about 1/2v dd ). an unselected input pin becomes the status set in bit 3 (vcohdmd) and bit 2 (vcoldmd) of the pll mode select register (pllmd). for the frequencies that can actually be input and the input amplitude, refer to chapter 25 electrical specifications . 467 user? manual u12790ej2v0ud chapter 20 frequency counter 20.1 function of frequency counter the frequency counter counts the intermediate frequency (if) of a tuner. it counts the intermediate frequency input to the fmifc or amifc pin for a specific time (1 ms, 4 ms, 8 ms, or open) with a 16-bit counter. the count value of the frequency counter is stored in the if counter register. for the range of the frequency that can be input to the fmifc and amifc pins, refer to chapter 25 electrical specifications . 20.2 configuration of frequency counter the frequency counter consists of the following hardware. table 20-1. configuration of frequency counter item configuration counter register if counter register (ifc) control registers if counter mode select register (ifcmd) if counter control register (ifcr) if counter gate judge register (ifcjg) 468 chapter 20 frequency counter user? manual u12790ej2v0ud figure 20-1. frequency counter block diagram (1) if counter input select block the if counter input select block selects the pin to be used from the fmifc and amifc pins, and the count mode. (2) gate time control block the gate time control block sets the gate time (count time). (3) start/stop control block the start/stop control block sets the count start of the if counter register and detects the end of counting. (4) if counter register block the if counter register block is a 16-bit register that counts up the frequency input in the set gate time. the count value is stored in the if counter register (ifcr). when the count value reaches ffffh, the if counter register holds ffffh at the next input, and stops counting. the value of this register is reset to 0000h after reset or in the stop mode. in the halt mode, it holds the current count value. internal bus ifc md0 ifc ck1 ifc ck0 ifc jg0 if counter mode select register if counter gate judge register if counter control register ifc md1 ifc res ifc st input select block start/stop control block gate time control block if counter register (ifc) block 2 2 fmifc amifc 469 chapter 20 frequency counter user s manual u12790ej2v0ud 20.3 registers controlling frequency counter the frequency counter is controlled by the following three registers. if counter mode select register (ifcmd) if counter control register (ifccr) if counter gate judge register (ifcjg) (1) if counter mode select register (ifcmd) this register selects the input pin of the frequency counter, and selects the mode and gate time (count time). this register is set by a 1-bit or 8-bit memory manipulation instruction. the value of this register is reset to 00h after reset or in the stop mode. in the halt mode, this register holds the value immediately before the halt mode was set. figure 20-2. format of if counter mode select register (ifcmd) ifcmd1 ifcmd0 selection of frequency counter pin and mode 0 0 fmifc amifc pins disabled note 1 0 1 amifc pin, amif count mode note 2 1 0 fmifc pin, fmif count mode note 2 1 1 fmifc pin, amif count mode note 2 ifcck1 ifcck0 selection of gate time 0 0 1 ms 0 1 4 ms 1 0 8 ms 1 1 open notes 1. the fmifc and amfic pins are used as port pins. 2. when using the amifc/p101 and fmifc/p102 pins to input signals to the frequency counter, set pm101 and pm102 to 1. caution any pin not selected by ifcmd is automatically set in the port mode. remark bits 4 to 7 are fixed to 0 by hardware. 7 0 6 0 5 0 4 0 ifcmd1 ifcmd0 ifcck1 ifcck0 symbol ifcmd r/w r/w after reset 00h address ffa9h <0> <1> <2> <3> 470 chapter 20 frequency counter user s manual u12790ej2v0ud (2) if counter control register (ifccr) this register sets the count start of the if counter register and clears the if counter register. ifccr is set by a 1-bit or 8-bit memory manipulation instruction. the value of this register is reset to 00h after reset and in the stop mode. in the halt mode, this register holds the value immediately before the halt mode was set. figure 20-3. format of if counter control register (ifccr) ifcst count start of if counter register 0 nothing is affected 1 counting starts ifcres clearance of data of if counter register 0 nothing is affected 1 data of if counter register cleared remark bits 2 to 7 are fixed to 0 by hardware. (3) if counter gate judge register (ifcjg) this register detects opening/closing of the gate of the frequency counter. the value of this register is reset to 00h after reset and in the stop mode. in the halt mode, this register holds the value immediately before the halt mode was set. figure 20-4. format of if counter gate judge register (ifcjg) ifcjg0 detection of opening/closing of gate of frequency counter 0 gate is closed 1 if gate time is set to other than open status until gate is closed after ifcst has been set to 1 if gate time is set to open status where gate is open as soon as it has been set to be opened remark bits 1 to 7 are fixed to 0 by hardware. caution ifcjg0 remains set even if the if counter register overflows and stops counting, until the set gate time expires. 7 0 6 0 5 0 4 0 3 0 2 0 ifcst ifcres symbol ifccr r/w w after reset 00h address ffach <0> <1> 7 0 6 0 5 0 4 0 3 0 2 0 1 0 ifcjg0 symbol ifcjg r/w r after reset 00h address ffabh <0> 471 chapter 20 frequency counter user s manual u12790ej2v0ud 20.4 operation of frequency counter (1) select the input pin, mode, and gate time by using the if counter mode select register (ifcmd). figure 20-5 shows a block diagram of input pin and mode selection. (2) set bit 0 (ifcres) of the if counter control register (ifccr) to 1, and clear the data of the if counter register. (3) set bit 1 (ifcst) of the if counter control register (ifccr) to 1. (4) the gate is opened only for the set gate time from when the 1 khz internal signal rises after ifcst is set. if the gate time is set to open, the gate is opened as soon as it has been specified to be opened. bit 0 (ifcjg0) of the if counter gate judge register (ifcjg) is automatically set to 1 as soon as ifcst has been set to 1. when the gate time has expired, bit 0 (ifcjg0) of the if counter gate judge register (ifcjg) is automatically cleared to 0. if it is specified that the gate be open, however, ifcjg0 is not automatically cleared. in this case, set a gate time. figure 20-6 shows the gate timing of the frequency counter. (5) the if counter register counts the frequency input to the selected fmifc or fmifc pin while the gate is open. if the fmifc pin is used in the fmif count mode, however, the input frequency is divided by half before it is counted input to the selected fmifc or amifc pin while the gate is open. the relationship between count value x (decimal), the input frequencies (f fmifc and f amifc ), and the gate time (t gate ) is shown below. fmif count mode (fmifc pin) f fmifc = x 2 (khz) t gate amif count mode (fmifc or amifc pin) f amifc = x (khz) t gate figure 20-5. block diagram of input pin and mode selection if counter register amp 1/2 amp amp fmifc amifc fmif count mode amif count mode amif count mode 472 chapter 20 frequency counter user s manual u12790ej2v0ud figure 20-6. gate timing of frequency counter (a) if gate time is set to 1, 4, or 8 ms (b) if gate is set to be open caution if counting is started by using ifcst while this gate is open, the gate is closed after an undefined time. to open the gate, therefore, do not set ifcst to 1. remark ifcst: bit 1 of the if counter control register (ifccr) ifcjg0: bit 0 of the if counter gate judge register (ifjg) ifcck1, ifcck0: bits 1 and 0 of the if counter mode select register (ifcmd) h l internal 1 khz ifcjg0 sets ifcst. ifcjg0 is automatically set at this point. counting starts. gate is opened at this point. clears ifcjg0 counting ends if gate time is 8 ms. gate time: 8 ms gate time: 1 ms gate time: 1 ms counting ends if gate time is 1 ms. counting ends if gate time is 4 ms. 1 ms 4 ms 8 ms open close open close open close gate time count period. if ifcst is set during this period, gate is closed after undefined time. h l internal 1 khz gate gate ifcck1 = ifcck0 = 1. gate is opened at this point. if gate is opened when ifcjg0 is opened, gate is closed after undefined time. ifcck1 = ifcck0 = 1 sets gate time by using ifcck1 and ifcck0 count period open close open close 473 chapter 20 frequency counter user s manual u12790ej2v0ud 20.5 notes on frequency counter (1) notes on using frequency counter because signals are input to the frequency counter from an input pin (fmifc or amifc pin) with an ac amplifier as shown in figure 20-7, cut the dc component of the input signals by using capacitor c. if the fmifc or amifc pin is selected by the if counter mode select register, switch sw1 turns on, and switch sw2 turns off. as a result, the voltage on the pin is about 1/2v dd . unless the voltage has risen to a sufficient intermediate level at this time, counting may not be performed normally because the ac amplifier is not in the normal operating range. therefore, make sure that sufficient wait time elapses after a pin has been selected and before counting is started (ifcst = 1). figure 20-7. frequency counter input pin circuit (2) notes in halt mode the fmifc and amifc pins hold the status immediately before the halt mode was set. to release the halt mode by using the interrupt of the frequency counter at this time, the following point must be noted. the gate will not be opened if the halt instruction is executed after counting has been started by ifcst before the gate is actually opened. therefore, wait for at least 1 ms before executing the halt instruction. figure 20-8. gate status when halt instruction is executed open close 1 ms max. timing to open gate sets ifcst interrupt request is not issued if halt instruction is executed during this period because gate is not opened. gate sw1 sw2 to internal counter v dd pll r c external frequency fmifc or amifc pin 474 chapter 20 frequency counter user s manual u12790ej2v0ud (3) error of frequency counter the error of the frequency counter includes the error of the gate time and the count error. (1) error of gate time the gate time of the frequency counter is created by dividing 6.3 mhz. therefore, if 6.3 mhz is shifted +x ppm, the gate time is also shifted x ppm. (2) count error the frequency counter counts the frequency at the rising edge of the input signal. if a high level is input to the pin when the gate is opened, therefore, one excess pulse is counted. when the gate is closed, however, counting is not affected by the status of the pin. therefore, the count error is maximum + 1 . 475 user? manual u12790ej2v0ud chapter 21 standby function 21.1 standby function and configuration 21.1.1 standby function the standby function is designed to decrease the power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. the halt mode stops the cpu operation clock, but the system clock oscillator continues oscillating. in this mode, the current consumption cannot be decreased as much as in the stop mode. the halt mode is effective for restarting immediately upon interrupt request generation and to carry out intermittent operations such as in watch applications. although the cpu stops operating, the peripheral functions can operate. to lower the current consumption, therefore, stop all unnecessary circuits before executing the halt instruction. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the system clock oscillator stops and the whole system stops. the cpu current consumption can be considerably decreased in this mode. data memory low-voltage hold (down to v dd = 2.3 v) is possible. thus, the stop mode is effective for holding data memory contents with ultra-low current consumption. if the supply voltage drops below 2.3 v, the system is reset by means of power-on clear reset. for reset, refer to chapter 22 reset function . because this mode can be released upon interrupt request generation, it enables intermittent operations to be carried out. however, because a wait time is necessary to secure the oscillation stabilization time after the stop mode is released, select the halt mode if it is necessary to start processing immediately upon interrupt request generation. all the functions stop operating in this mode. some registers of the pll frequency synthesizer and frequency counter are reset, but the other functions are stopped with their current status held. cautions 1. when proceeding to the stop mode, be sure to stop the peripheral hardware operations before executing the stop instruction. 2. the following sequence is recommended for power consumption reduction of the a/d converter: first clear bit 7 (adcs3) of adm3 to 0 to stop the a/d conversion operation, then execute the halt or stop instruction. 476 chapter 21 standby function user? manual u12790ej2v0ud 21.1.2 standby function control register a wait time from when the stop mode is released upon interrupt request generation until the oscillation stabilizes is controlled by the oscillation stabilization time select register (osts). osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 04h. figure 21-1. format of oscillation stabilization time select register (osts) remark f x : system clock oscillation frequency ( ): f x = 6.3 mhz caution the wait time when the stop mode is released does not include the time required for the clock oscillation to start after the stop mode has been released (see ??in the figure below), regardless of whether the mode has been released by the reset signal or an interrupt request. address fffah 04h after reset r/w r/w 0 0 0 0 1 selection of oscillation stabilization time when stop mode is released 2 12 /f x osts2 7 0 symbol osts 6 0 5 0 4 0 3 0 2 osts2 1 osts1 0 osts0 0 0 1 1 0 other than above osts1 0 1 0 1 0 osts0 setting prohibited 2 14 /f x 2 15 /f x 2 16 /f x 2 17 /f x (650 s) (2.60 ms) (5.20 ms) (10.4 ms) (20.8 ms) stop mode release x1 pin voltage waveform v ss a 477 chapter 21 standby function user s manual u12790ej2v0ud 21.2 standby function operations 21.2.1 halt mode (1) halt mode setting and operating status the halt mode is set by executing the halt instruction. the operating status in the halt mode is described below. table 21-1. halt mode operating status item status clock generator system clock oscillates. clock supply to cpu stopped. cpu stops operating. port hold status before halt mode was set. 16-bit timer/event counter 0 hold operation before halt mode was set and can operate. 8-bit timer/event counters 50, 51 basic timer watchdog timer buzzer output controller a/d converter holds operation performed when halt mode was set. however, comparison cannot be performed correctly in a/d conversion operation mode. in power-fail comparison mode, operation is as follows depending on setting of bit 5 (pfhrm3) of power-fail comparison mode register 3 (pfm3): pfhrm3 = 0: comparison cannot be performed normally. pfhrm3 = 1: power-fail comparison operation can be performed. serial interface sio0, sio3, hold operation performed when halt mode was set and can operate. uart0 note 1 sio1 holds operation performed when halt mode was set. however, transfer is continued with erroneous data if serial clock is supplied in automatic transfer mode. iebus controller note 2 hold operation before halt mode was set and can operate. external interrupt pll frequency synthesizer frequency counter holds operation performed before halt mode was set. however, operation is not performed correctly even though it is continued. power-on clear circuit reset when voltage of less than 3.5 v is detected. notes 1. pd178076, 178078, and 178f098 only. 2. pd178096a, 178098a, and 178f098 only. 478 chapter 21 standby function user s manual u12790ej2v0ud (2) halt mode release the halt mode can be released by the following three sources. (a) release upon unmasked interrupt request generation when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. if disabled, the next address instruction is executed. figure 21-2. halt mode release upon interrupt generation remarks 1. the broken lines indicate the case when the interrupt request which has released the standby status is acknowledged. 2. the wait time is as follows: when vectored interrupt servicing is carried out: 8 to 9 clocks when vectored interrupt servicing is not carried out: 2 to 3 clocks (b) release upon non-maskable interrupt request generation when a non-maskable interrupt is generated, the halt mode is released and vectored interrupt servicing is carried out regardless of whether interrupt acknowledgment is enabled or disabled. halt instruction wait standby release signal operating mode clock halt mode wait oscillation operating mode interrupt request 479 chapter 21 standby function user s manual u12790ej2v0ud (c) release by reset input if a reset signal is input, the halt mode is released. as is the case with a normal reset operation, the program is executed after branch to the reset vector address. figure 21-3. halt mode release by reset input remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 6.3 mhz table 21-2. operation after halt mode release release source mk pr ie isp operation maskable interrupt 0 0 0 next address instruction execution request 0 0 1 interrupt servicing execution 0 1 0 1 next address instruction execution 01 0 0 1 1 1 interrupt servicing execution 1 halt mode held non-maskable interrupt interrupt servicing execution request reset input reset processing remark : don't care halt instruction reset signal operating mode clock reset period halt mode oscillation oscillation stop oscillation stabilization wait status operating mode oscillation wait (2 17 /f x : 20.8 ms) 480 chapter 21 standby function user s manual u12790ej2v0ud 21.2.2 stop mode (1) stop mode setting and operating status the stop mode is set by executing the stop instruction. cautions 1. when the stop mode is set, the x1 pin is pulled down to gnd0, and the x2 pin is internally pulled up to v dd to minimize the leakage current of the crystal oscillator. 2. because the interrupt request signal is used to release the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately released if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction, and the operating mode is set after the wait set using the oscillation stabilization time select register (osts). the operating status in the stop mode is described below. table 21-3. stop mode operating status item status clock generator system clock stopped. clock supply to cpu stopped. cpu stops operating. ports hold status before stop mode was set. 16-bit timer/event counter 0 stop operating and cannot operate. 8-bit timer/event counters 50, 51 basic timer watchdog timer buzzer output controller a/d converter serial interface sio0, sio1, sio3, uart0 note 1 iebus controller note 2 external interrupt can operate. pll frequency synthesizer stop operating and cannot operate. frequency counter power-on clear circuit reset generated when 2.3 v or less is detected. notes 1. pd178076, 178078, and 178f098 only. 2. pd178096a, 178098a, and 178f098 only. 481 chapter 21 standby function user s manual u12790ej2v0ud remark the broken lines indicate the case when the interrupt request which has released the standby status is acknowledged. (2) stop mode release the stop mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. if interrupt request acknowledgment is enabled after the lapse of the oscillation stabilization time, vectored interrupt servicing is carried out. if interrupt request acknowledgment is disabled, the next address instruction is executed. figure 21-4. stop mode release by interrupt request generation stop instruction wait (time set by osts) oscillation stabilization wait status operating mode oscillation operating mode stop mode oscillation stop oscillation standby release signal clock interrupt request 482 chapter 21 standby function user s manual u12790ej2v0ud (b) release by reset input if a reset signal is input, the stop mode is released, and after the lapse of oscillation stabilization time, the reset operation is carried out. figure 21-5. release by stop mode reset input remarks 1. f x : system clock oscillation frequency 2. ( ): f x = 6.3 mhz table 21-4. operation after stop mode release release source mk pr ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt servicing execution 0 1 0 1 next address instruction execution 01 0 0 1 1 1 interrupt servicing execution 1 stop mode held reset input reset processing remark : don't care reset signal operating mode clock reset period stop mode oscillation stop oscillation stabilization wait status operating mode oscillation wait (2 17 /f x : 20.8 ms) stop instruction oscillation 483 user? manual u12790ej2v0ud chapter 22 reset function 22.1 reset function the following three operations are available to generate the reset signal. (1) external reset input by reset pin (2) internal reset by inadvertent program loop time detection of watchdog timer (3) internal reset by power-on clear (poc) (1) external reset input by reset pin when a low level is input to the reset pin, the device is reset, and each hardware unit enters the status shown in table 22-1. while the reset signal is input and during the oscillation stabilization time immediately after the reset signal has been deasserted, each pin goes into a high-impedance state (however, the p130 through p137 pins go low, and the vcoh and vcol pins are pulled down). the reset signal is deasserted when a high level is input to the reset pin, and program execution is started after the oscillation stabilization time (2 17 /f x ) has elapsed. (2) internal reset by inadvertent program loop time detection of watchdog timer reset is effected and each hardware unit enters the status shown in table 22-1 when the watchdog timer overflows. while reset is effected and during the oscillation stabilization time immediately after the effect of reset has been cleared, each pin goes into a high-impedance state (however, the p130 to p137 pins go low, and the vcoh and vcol pins are pulled down). reset by the watchdog timer is cleared immediately after reset has been effected, and program execution is started after the oscillation stabilization time (2 17 /f x ) has elapsed. (3) internal reset by power-on clear (poc) reset is effected by means of power-on clear under the following conditions. if supply voltage is less than 3.5 v note on power application if supply voltage drops to less than 2.3 v note in stop mode if supply voltage drops to less than 3.5 v note (including in halt mode) when these power-on clear reset conditions are satisfied, reset is effected, and each hardware unit enters the status shown in table 22-1. while the reset signal is input and during the oscillation stabilization time immediately after the reset signal has been deasserted, each pin goes into a high-impedance state (the p130 to p137 pins go low, however). reset by power-on clear is cleared if the supply voltage rises beyond a specific level, and program execution is started after the oscillation stabilization time (2 17 /f x ) has elapsed. note these voltage values are maximum values. actually, reset is effected at a voltage lower than these. 484 chapter 22 reset function user? manual u12790ej2v0ud cautions 1. for an external reset, input a low level to the reset pin for 10 s or more. 2. during reset input, system clock oscillation remains stopped. 3. when the stop mode is released by reset input, the stop mode register contents are held during reset input. however, the i/o port pins become high-impedance. output port pins (p130 to p137) become low level regardless of the previous status. figure 22-1. reset function block diagram reset count clock reset controller watchdog timer stop over- flow reset signal interrupt function power-on clear circuit in stop mode 485 chapter 22 reset function user s manual u12790ej2v0ud (b) in stop mode reset internal reset signal i/o port pin delay delay high impedance x1 normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) stop status (oscillation stop) stop instruction execution output port pin (p130 to p137) figure 22-2. timing of reset by reset input (a) in normal operating mode reset internal reset signal i/o port pin delay delay high impedance x1 normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) output port pin (p130 to p137) 486 chapter 22 reset function user s manual u12790ej2v0ud figure 22-3. timing of reset due to watchdog timer overflow x1 normal operation watchdog timer overflow internal reset signal i/o port pin reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) high impedance output port pin (p130 to p137) 487 chapter 22 reset function user s manual u12790ej2v0ud figure 22-4. timing of reset by power-on clear (a) at power-on (b) in stop mode (c) in normal operating mode (including halt mode) high impedance i/o port pin reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 v dd internal reset signal power-on clear voltage (3.5 v) output port pin (p130 to p137) 4.5 v 3.5 v 2.3 v l high impedance normal operation i/o port pin reset period (oscillation stop) stop status (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 v dd internal reset signal power-on clear voltage (2.3 v) output port pin (p130 to p137) 4.5 v 3.5 v 2.3 v stop instruction execution i/o port pin x1 v dd power-on clear voltage (3.5 v) output port pin (p130 to p137) 4.5 v 3.5 v 2.3 v reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) internal reset signal high impedance normal operation 488 chapter 22 reset function user? manual u12790ej2v0ud table 22-1. hardware status after reset (1/3) hardware status after reset program counter (pc) note 1 contents of reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) undefined ram data memory undefined note 2 general-purpose register undefined note 2 ports (output latches) ports 0, 2, 3, 7, 10, 12, 13 (p0, p2, p3, p7, p10, p12, p13) 00h ports 4 to 6 (p4 to p6) undefined port mode registers (pm0, pm2 to pm7, pm10, pm12) ffh processor clock control register (pcc) 04h oscillation stabilization time select register (osts) 04h memory size select register (ims) cfh note 3 internal expansion ram size select register (ixs) 0ch note 4 16-bit timer/event counter 0 timer register (tm0) 0000h capture/compare registers 00, 01 (cr00, cr01) undefined mode control register 0 (tmc0) 00h prescaler mode register 0 (prm0) 00h capture/compare control register 0 (crc0) 00h output control register 0 (crc0) 00h 8-bit timer/event counters counters 50, 51 (tm50, tm51) 00h 50, 51 compare registers 50, 51 (cr50, cr51) undefined clock select registers 50, 51 (tcl50, tcl51) 00h mode control registers 50, 51 (tmc50, tmc51) 00h notes 1. during reset input or oscillation stabilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. the status before reset is held even after reset in the standby mode. 3. the initial value is cfh. set the following value to this register according to the product. pd178076, 178096a: cch pd178078, 178098a: cfh pd178f098: value corresponding to mask rom version 4. the initial value is 0ch. set the following value to this register according to the product. pd178076, 178096a: 0ah pd178078, 178098a: 08h pd178f098: value corresponding to mask rom version 489 chapter 22 reset function user s manual u12790ej2v0ud table 22-1. hardware status after reset (2/3) hardware status after reset watchdog timer clock select register (wdcs) 00h mode register (wdtm) 00h buzzer output beep0 frequency select register 0 (beepcl0) 00h controller buz clock output control register (cks) 00h serial interface sio0 shift register 0 (sio0) undefined slave address register 0 (sva0) undefined clock select register 0 (scl0) 08h operating mode register 0 (csim0) 00h serial bus interface control register 0 (sbic0) 00h interrupt timing specification register 0 (sint0) 00h sio1 shift register 1 (sio1) undefined operating mode register 1 (csim1) 00h automatic data transmit/receive address pointer register (adtp) 00h automatic data transmit/receive control register (adtc) 00h automatic data transmit/receive transfer interval specification register (adti) 00h sio3 shift register 3 (sio3) undefined operating mode register 3 (csim3) 00h uart0 note 1 asynchronous serial interface mode register 0 (asim0) 00h asynchronous serial interface status register 0 (asis0) 00h baud rate generator control register 0 (brgc0) 00h transmit shift register 0/receive buffer register 0 (txs0, rxb0) ffh iebus controller note 2 iebus control register 0 (bcr0) 00h iebus unit address register (uar) 0000h iebus slave address register (sar) 0000h iebus other unit address register (par) 0000h iebus control data register (cdr) 01h iebus telegraph length register (dlr) 01h iebus data register (dr) 00h iebus unit status register (usr) 00h iebus interrupt status register (isr) 00h iebus slave status register (ssr) 41h iebus communication success counter (scr) 01h iebus transmission counter (ccr) 20h notes 1. pd178076, 178078, and 178f098 only 2. pd178096a, 178098a, and 178f098 only 490 chapter 22 reset function user s manual u12790ej2v0ud table 22-1. hardware status after reset (3/3) hardware status after reset a/d converter mode register 3 (adm3) 00h a/d conversion result register 3 (adcr3) undefined analog input channel specification register 3 (ads3) 00h power-fail comparison mode register 3 (pfm3) 00h power-fail comparison threshold value register 3 (pft3) 00h interrupt request flag registers (if0l, if0h, and if1l) 00h mask flag registers (mk0l, mk0h, and mk1l) ffh priority specification flag registers (pr0l, pr0h, and pr1l) ffh external interrupt rising edge enable register (egp) 00h external interrupt falling edge enable register (egn) 00h pll frequency synthesizer pll mode select register (pllmd) 00h pll reference mode register (pllrf) 0fh pll unlock ff judge register (pllul) held note 1 pll data registers (pllrh, pllrl, and pllr0) undefined pll data transfer control register (pllns) 00h frequency counter if counter mode select register (ifcmd) 00h if counter gate judge register (ifcjg) 00h if counter control register (ifccr) 00h if counter data register (ifcr) 0000h power-on clear poc status register (pocs) held note 2 vm45 control register (vm45c) 00h notes 1. undefined only at power-on clear reset 2. 03h only at power-on clear reset 491 chapter 22 reset function user s manual u12790ej2v0ud 22.2 power failure detection function if reset is effected by means of power-on clear, bit 0 (pocm) of the poc status register (pocs) is set to 1. if reset is effected by the reset pin or the watchdog timer, however, pocm holds the previous status. a power failure status can be detected by detecting pocm after reset by power-on clear has been released (after program execution has been started from address 0000h). figure 22-5. format of poc status register (pocs) pocm detection of power-on clear occurrence status 0 power-on clear does not occur 1 note reset is effected by power-on clear note the value of this register is set to 03h only when reset is effected by power-on clear. it is not reset by the reset pin or watchdog timer. remark the values of the special-function registers, other than pocs, are the same as the values after a reset effected by means of power-on clear. 7 0 6 0 5 0 4 0 3 0 2 0 1 vm45 pocm symbol pocs after reset held note r/w r&reset address ff1bh 0 492 chapter 22 reset function user s manual u12790ej2v0ud 22.3 4.5 v voltage detection function this function is used to detect a voltage drop on the v dd pin below 4.5 v (4.5 v 0.3 v). if the voltage on the v dd pin drops below 4.5 v (4.5 v 0.3 v), bit 1 (vm45) of the poc status register (pocs) is set. at the same time, this status can be monitored by the vm45/p30 pin. therefore, the power to the other peripheral units can be controlled when a voltage of less than 4.5 v is detected. note, however, that this 4.5 v voltage detection function does not cause an internal reset. figure 22-6. format of poc status register (pocs) vm45 detection of voltage level of v dd pin 0 not detected if v dd pin is less than 4.5 v (4.3 0.3 v) 1 detected if v dd pin is less than 4.5 v (4.3 0.3 v) note the value of this register is set to 03h only at power-on clear reset, and is not reset by the reset pin or watchdog timer. remark the values of the special-function registers other than pocs after reset are the same as the values at power-on clear. the status detected (not detected) by vm45 can be output to (monitored by) the vm45/p30 pin under control of the vm45 control register (vm45c). figure 22-7. format of vm45 control register (vm45c) vm45c1 enable/disable of output of vm45 (v dd 4.5 v monitor) 0 output of vm45 to vm45/p30 pin disabled (port function) 1 note output of vm45 to vm45/p30 pin enabled vm45c0 selection of output of vm45 (v dd 4.5 v monitor) 0 high level output 1 low level output note when the vm45/p30 pin is used for vm45 output, reset the output latches of bit 0 (pm30) of pm3 and bit 0 (p30) of p3 to 0. 7 0 6 0 5 0 4 0 3 0 2 0 vm45c1 symbol vm45c after reset 00h r/w r/w vm45c0 <0> <1> address ff19h 7 0 6 0 5 0 4 0 3 0 2 0 1 vm45 0 pocm symbol pocs after reset held note r/w r&reset address ff1bh 493 user? manual u12790ej2v0ud chapter 23 pd178f098 the pd178f098 is provided with a flash memory to/from which data can be written/erased with the device mounted on the board. the differences between the flash memory version ( pd178f098) and mask rom versions ( pd178076, 178078, 178096a, and 178098a) are shown in table 23-1. table 23-1. differences between pd178f098 and mask rom versions item pd178f098 pd178076, 178078 pd178096a, 178098a internal memory rom structure flash memory mask rom rom capacity 60 kb pd178076: 48 kb pd178096a: 48 kb pd178078: 60 kb pd178098a: 60 kb expansion ram 2048 bytes pd178076: 1024 bytes pd178096a: 1024 bytes capacity pd178078: 2048 bytes pd178098a: 2048 bytes internal rom capacity selected by equivalent to mask rom pd178076: 0ah pd178096a: 0ah memory size select register (ims) version pd178078: 08h pd178098a: 08h internal expansion ram capacity equivalent to mask rom pd178076: cch pd178096a: cch selected by internal expansion ram version pd178078: cfh pd178098a: cfh size select register (ixs) serial interface 4 channels (sio0, sio1, sio3, uart0) 3 channels (sio0, sio1, sio3) iebus controller provided not provided provided ic pin not provided provided v pp pin provided not provided 494 chapter 23 pd178f098 user? manual u12790ej2v0ud 23.1 memory size select register the internal memory capacity of the pd178f098 can be changed using the memory size select register (ims). by using this register, the memory of the pd178f098 can be mapped in the same manner as a mask rom version with a different internal memory capacity. ims is set by an 8-bit memory manipulation instruction. this register is set to cfh after reset. be sure to set ims to cch or cfh. figure 23-1. format of memory size select register (ims) ram2 ram1 ram0 selection of internal high-speed ram capacity 1 1 0 1024 bytes other than above setting prohibited ram3 ram2 ram1 ram0 selection of internal rom capacity 110048 kb 111160 kb other than above setting prohibited table 23-2 shows the setting of ims to perform the same memory mapping as that of a mask rom version. table 23-2. set value of memory size select register target version set value of ims pd178076, 178096a cch pd178078, 178098a cfh 7 ram2 6 ram1 5 ram0 4 0 3 rom3 2 rom2 1 rom1 0 rom0 symbol ims after reset cfh r/w r/w address fff0h 495 chapter 23 pd178f098 user? manual u12790ej2v0ud 23.2 internal expansion ram size select register the internal ram expansion capacity of the pd178f098 can be changed using the internal expansion ram size select register (ixs). by using this register, the memory of the pd178f098 can be mapped in the same manner as a mask rom version with a different internal expansion ram capacity. ixs is set by an 8-bit memory manipulation instruction. this register is set to 0ch after reset. be sure to set ixs to 0ah or 08h. figure 23-2. format of internal expansion ram size select register (ixs) ixram4 ixram3 ixram2 ixram1 ixram0 selects internal expansion ram capacity 01000 2048 bytes 01010 1024 bytes other than above setting prohibited table 23-3 shows the setting of ixs to perform the same memory mapping as that of a mask rom version. table 23-3. set value of internal expansion ram size select register target version set value of ixs pd178076, 178096a 0ah pd178078, 178098a 08h 7 0 6 0 5 0 4 ixram4 3 i xram3 2 i xram2 1 i xram1 0 i xram0 symbol ixs after reset 0ch r/w r/w address fff4h 496 chapter 23 pd178f098 user s manual u12790ej2v0ud 23.3 flash memory features flash memory programming is performed by connecting a dedicated flash programmer (flashpro iii (part no. fl- pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)) to the target system with the flash memory mounted on the target system (on-board write). a flash memory writing adapter (program adapter), which is a target board used exclusively for programming, is also provided. remark fl-pr3, fl-pr4, and the program adapter are products of naito densei machida mfg. co., ltd. (tel +81-45-475-4191). programming using flash memory has the following advantages. ? software can be modified after the microcontroller is solder-mounted on the target system. ? distinguishing software facilities low-quantity, varied model production ? easy data adjustment when starting mass production 23.3.1 programming environment the following shows the environment required for pd178f098 flash memory programming. when flashpro iii (part no. fl-pr3, pg-fp3) or flashpro iv (part no. fl-pr4, pg-fp4) is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. communication between the host machine and flash programmer is performed via rs-232c/usb (rev. 1.1). for details, refer to the manuals for flashpro iii/flashpro iv. remark usb is supported by flashpro iv only. figure 23-3. environment for writing program to flash memory host machine rs-232c usb dedicated flash programmer pd178f098 v pp v dd v ss reset sio/uart 497 chapter 23 pd178f098 user s manual u12790ej2v0ud 23.3.2 communication mode use the communication mode shown in table 23-4 to perform communication between the dedicated flash programmer and pd178f098. table 23-4. communication mode list communication type setting note 1 pins used number mode comm port sio clock cpu flash clock multiple of v pp clock rate pulses 3-wire serial i/o sio ch-0 100 hz to optional 1 to 1.0 p72/sck3 0 (3 wired, sync.) 1.25 mhz note 2 5 mhz note 2 p71/so3 p70/si3 uart (uart0) uart ch-0 4,800 to optional 1 to 1.0 p75/txd0 8 (async.) 76,800 bps notes 2, 3 5 mhz note 2 p74/rxd0 notes 1. selection items for type settings on the dedicated flash programmer (flashpro iii (part no. fl-pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)). 2. the possible setting range differs depending on the voltage. for details, see chapter 25 elec- trical specifications . 3. because factors other than the baud rate error, such as the signal waveform slew, also affect uart communication, thoroughly evaluate the slew as well as the baud rate error. figure 23-4. communication mode selection format 10 v v pp v pp pulses flash memory write mode reset v dd gnd v dd gnd 498 chapter 23 pd178f098 user s manual u12790ej2v0ud figure 23-5. example of connection with dedicated flash programmer (a) 3-wire serial i/o (b) uart note connect this pin when the system clock is supplied from the dedicated flash programmer. if a resonator is already connected to the x1 pin, do not connect to the clk pin. caution the v dd and v dd port pins, even if already connected to the power supply, must be connected to the vdd pin of the dedicated flash programmer. when using the power supply connected to the v dd and v dd port pins, supply voltage before starting programming. dedicated flash programmer vpp1 vdd reset sck so si clk note gnd v pp v dd , v dd port reset sck3 si3 so3 x1 gnd0 to gnd2, gndport pd178f098 dedicated flash programmer vpp1 vdd reset so (t x d) si (r x d) clk note gnd v pp v dd , v dd port reset r x d0 t x d0 x1 gnd0 to gnd2, gndport pd178f098 499 chapter 23 pd178f098 user s manual u12790ej2v0ud when flashpro iii/flashpro iv is used as a dedicated flash programmer, the following signals are generated for the pd178f098. for details, refer to the manual of flashpro iii/flashpro iv. table 23-5. pin connection list signal name i/o pin function pin name 3-wire serial i/o uart vpp1 output write voltage v pp vpp2 ?? ? vdd i/o v dd voltage generation/ v dd , v dd port note note voltage monitoring gnd ? ground gnd0 to gnd2, gndport clk output clock output x1 reset output reset signal reset si (rxd) input reception signal so3/txd0 so (txd) output transmit signal si3/rxd0 sck output transfer clock sck3 hs input handshake signal ? note v dd voltage must be supplied before programming is started. remark : pin must be connected. : if the signal is supplied on the target board, pin does not need to be connected. : pin does not need to be connected. 500 chapter 23 pd178f098 user? manual u12790ej2v0ud 23.3.3 on-board pin handling when performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. an on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases. 501 chapter 23 pd178f098 user s manual u12790ej2v0ud (1) signal conflict if the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. to prevent this, isolate the connection with the other device or set the other device to the output high-impedance status. figure 23-7. signal conflict (input pin of serial interface) (2) abnormal operation of other device if the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), a signal is output to the device, and this may cause an abnormal operation. to prevent this abnormal operation, isolate the connection with the other device or set so that the input signals to the other device are ignored. figure 23-8. abnormal operation of other device input pin signal conflict connection pin of dedicated flash programmer other device output pin in the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict, therefore, isolate the signal of the other device. pd178f098 pin connection pin of dedicated flash programmer other device input pin if the signal output by the pd178f098 affects another device in the flash memory programming mode, isolate the signals of the other device. pin connection pin of dedicated flash programmer other device input pin if the signal output by the dedicated flash programmer affects another device in the flash memory programming mode, isolate the signals of the other device. pd178f098 pd178f098 502 chapter 23 pd178f098 user s manual u12790ej2v0ud 503 chapter 23 pd178f098 user s manual u12790ej2v0ud 23.3.4 connection of adapter for flash writing the following figures show examples of the recommended connection when the adapter for flash writing is used. figure 23-10. wiring example for flash writing adapter in 3-wire serial i/o mode pd178f098 gnd vdd vdd2(lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (3.5 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 504 chapter 23 pd178f098 user s manual u12790ej2v0ud figure 23-11. wiring example for flash writing adapter in uart pd178f098 gnd vdd vdd2(lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (3.5 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 505 user? manual u12790ej2v0ud chapter 24 instruction set this chapter describes each instruction set of the pd178078 and 178098a subseries as list tables. for details of the operation and operation code of each instruction, refer to the separate document 78k/0 series instruction user? manual (u12326e) . 506 chapter 24 instruction set user? manual u12790ej2v0ud 24.1 conventions 24.1.1 operand identifiers and description method operands are written in the ?perand?column of each instruction in accordance with the description of the instruction operand identifiers (refer to the assembler specifications for details). when there are two or more descriptions, select one of them. uppercase letters and the symbols #, !, $, and [ ] are keywords and must be written as they are. each symbol has the following meaning. #: immediate data specification !: absolute address specification $: relative address specification [ ]: indirect address specification in the case of immediate data, write an appropriate numeric value or a label. when using a label, be sure to write the #, !, $, and [ ] symbols. for the operand register symbols, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used. table 24-1. operand symbols and descriptions symbol description r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7), rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special-function register symbol note sfrp special-function register symbol (16-bit manipulatable register, even addresses only) note saddr fe20h to ff1fh immediate data or labels saddrp fe20h to ff1fh immediate data or labels (even addresses only) addr16 0000h to ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) addr11 0800h to 0fffh immediate data or labels addr5 0040h to 007fh immediate data or labels (even addresses only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh cannot be accessed with these operands. remark for special-function register symbols, refer to table 3-4 special-function register list . 507 chapter 24 instruction set user? manual u12790ej2v0ud 24.1.2 description of ?peration?column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag nmis: non-maskable interrupt servicing flag ( ): memory contents indicated by address or register contents in parentheses h , l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 24.1.3 description of ?lag operation?column (blank): not affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored 508 chapter 24 instruction set user? manual u12790ej2v0ud 24.2 operation list clocks flag note 1 note 2 zaccy mov r, #byte 2 4 r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 7 sfr byte a, r note 3 12 a r r, a note 3 12 r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 5 a sfr sfr, a 2 5 sfr a a, !addr16 3 8 9 a (addr16) !addr16, a 3 8 9 (addr16) a psw, #byte 3 7 psw byte a, psw 2 5 a psw psw, a 2 5 psw a a, [de] 1 4 5 a (de) [de], a 1 4 5 (de) a a, [hl] 1 4 5 a (hl) [hl], a 1 4 5 (hl) a a, [hl + byte] 2 8 9 a (hl + byte) [hl + byte], a 2 8 9 (hl + byte) a a, [hl + b] 1 6 7 a (hl + b) [hl + b], a 1 6 7 (hl + b) a a, [hl + c] 1 6 7 a (hl + c) [hl + c], a 1 6 7 (hl + c) a xch a, r note 3 12 a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 6 a ? sfr a, !addr16 3 8 10 a ? (addr16) a, [de] 1 4 6 a ? (de) a, [hl] 1 4 6 a ? (hl) a, [hl + byte] 2 8 10 a ? (hl + byte) a, [hl + b] 2 8 10 a ? (hl + b) a, [hl + c] 2 8 10 a ? (hl + c) notes 1. when the internal high-speed ram area is accessed or an instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except "r = a" remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to the internal rom program. instruction group mnemonic operands bytes operation 8-bit data transfer 509 chapter 24 instruction set user? manual u12790ej2v0ud mnemonic operands bytes operation instruction group 16-bit data transfer 8-bit operation clocks flag note 1 note 2 zaccy movw rp, #word 3 6 rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 8 ax sfrp sfrp, ax 2 8 sfrp ax ax, rp note 3 1 4 ax rp rp, ax note 3 1 4 rp ax ax, !addr16 3 10 12 ax (addr16) !addr16, ax 3 10 12 (addr16) ax xchw ax, rp note 3 1 4 ax ? rp add a, #byte 2 4 a, cy a + byte saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 2 4 a, cy a + r r, a 2 4 r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 a, cy a + (addr16) a, [hl] 1 4 5 a, cy a + (hl) a, [hl + byte] 2 8 9 a, cy a + (hl + byte) a, [hl + b] 2 8 9 a, cy a + (hl + b) a, [hl + c] 2 8 9 a, cy a + (hl + c) addc a, #byte 2 4 a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 2 4 a, cy a + r + cy r, a 2 4 r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 a, cy a + (addr16) + cy a, [hl] 1 4 5 a, cy a + (hl) + cy a, [hl + byte] 2 8 9 a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 a, cy a + (hl + b) + cy a, [hl + c] 2 8 9 a, cy a + (hl + c) + cy notes 1. when the internal high-speed ram area is accessed or an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except "r = a" remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to the internal rom program. 510 chapter 24 instruction set user? manual u12790ej2v0ud mnemonic operands bytes operation instruction group 8-bit operation clocks flag note 1 note 2 zaccy sub a, #byte 2 4 a, cy a ?byte saddr, #byte 3 6 8 (saddr), cy (saddr) ?byte a, r note 3 2 4 a, cy a ?r r, a 2 4 r, cy r ?a a, saddr 2 4 5 a, cy a ?(saddr) a, !addr16 3 8 9 a, cy a ?(addr16) a, [hl] 1 4 5 a, cy a ?(hl) a, [hl + byte] 2 8 9 a, cy a ?(hl + byte) a, [hl + b] 2 8 9 a, cy a ?(hl + b) a, [hl + c] 2 8 9 a, cy a ?(hl + c) subc a, #byte 2 4 a, cy a ?byte ?cy saddr, #byte 3 6 8 (saddr), cy (saddr) ?byte ?cy a, r note 3 2 4 a, cy a ?r ?cy r, a 2 4 r, cy r ?a ?cy a, saddr 2 4 5 a, cy a ?(saddr) ?cy a, !addr16 3 8 9 a, cy a ?(addr16) ?cy a, [hl] 1 4 5 a, cy a ?(hl) ?cy a, [hl + byte] 2 8 9 a, cy a ?(hl + byte) ?cy a, [hl + b] 2 8 9 a, cy a ?(hl + b) ?cy a, [hl + c] 2 8 9 a, cy a ?(hl + c) ?cy and a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a [hl] a, [hl + byte] 2 8 9 a a [hl + byte] a, [hl + b] 2 8 9 a a [hl + b] a, [hl + c] 2 8 9 a a [hl + c] notes 1. when the internal high-speed ram area is accessed or an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except "r = a" remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to the internal rom program. 511 chapter 24 instruction set user? manual u12790ej2v0ud mnemonic operands bytes operation instruction group clocks flag note 1 note 2 zaccy or a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) a, [hl + c] 2 8 9 a a (hl + c) xor a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) a, [hl + c] 2 8 9 a a (hl + c) cmp a, #byte 2 4 a ?byte saddr, #byte 3 6 8 (saddr) ?byte a, r note 3 24 a r r, a 2 4 r ?a a, saddr 2 4 5 a ?(saddr) a, !addr16 3 8 9 a ?(addr16) a, [hl] 1 4 5 a ?(hl) a, [hl + byte] 2 8 9 a ?(hl + byte) a, [hl + b] 2 8 9 a ?(hl + b) a, [hl + c] 2 8 9 a ?(hl + c) notes 1. when the internal high-speed ram area is accessed or an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except "r = a" remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to the internal rom program. 8-bit operation 512 chapter 24 instruction set user? manual u12790ej2v0ud [hl] 2 10 12 [hl] 2 10 12 24 24 mnemonic operands bytes operation instruction group 16-bit operation multiply/ divide increment/ decrement rotate clocks flag note 1 note 2 zaccy addw ax, #word 3 6 ax, cy ax + word subw ax, #word 3 6 ax, cy ax ?word cmpw ax, #word 3 6 ax ?word mulu x 2 16 ax a x divuw c 2 25 ax (quotient), c (remainder) ax c inc r12 r r + 1 saddr 2 4 6 (saddr) (saddr) + 1 dec r12 r r ?1 saddr 2 4 6 (saddr) (saddr) ?1 incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ?1 ror a, 1 1 2 (cy, a 7 a 0 , a m? a m ) 1 time rol a, 1 1 2 (cy, a 0 a 7 , a m+1 a m ) 1 time rorc a, 1 1 2 (cy a 0 , a 7 cy, a m? a m ) 1 time rolc a, 1 1 2 (cy a 7 , a 0 cy, a m+1 a m ) 1 time ror4 a 3-0 (hl) 3-0 , (hl) 7-4 a 3-0 , (hl) 3-0 (hl) 7-4 rol4 a 3-0 (hl) 7-4 , (hl) 3-0 a 3-0 , (hl) 7-4 (hl) 3-0 adjba decimal adjust accumulator after addition adjbs decimal adjust accumulator after subtract mov1 cy, saddr.bit 3 6 7 cy (saddr.bit) cy, sfr.bit 3 7 cy sfr.bit cy, a.bit 2 4 cy a.bit cy, psw.bit 3 7 cy psw.bit cy, [hl].bit 2 6 7 cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 8 sfr.bit cy a.bit, cy 2 4 a.bit cy psw.bit, cy 3 8 psw.bit cy [hl].bit, cy 2 6 8 (hl).bit cy notes 1. when the internal high-speed ram area is accessed or an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to the internal rom program. bit manipulate bcd adjust 513 chapter 24 instruction set user? manual u12790ej2v0ud mnemonic operands bytes operation instruction group bit manipulate clocks flag note 1 note 2 zaccy and1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw.bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 cy cy (hl).bit or1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw.bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 cy cy (hl).bit xor1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw. bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 cy cy (hl).bit set1 saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 8 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 2 6 psw.bit 1 [hl].bit 2 6 8 (hl).bit 1 clr1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 8 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 2 6 psw.bit 0 [hl].bit 2 6 8 (hl).bit 0 set1 cy 1 2 cy 11 clr1 cy 1 2 cy 00 not1 cy 1 2 cy cy notes 1. when the internal high-speed ram area is accessed or an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to the internal rom program. 514 chapter 24 instruction set user? manual u12790ej2v0ud instruction group !addr16 3 7 [addr5] 1 6 retb 16 rrr 16 rp 1 4 rp 1 4 push uncondi- tional branch stack manipulate conditional branch mnemonic operands bytes operation clocks flag note 1 note 2 zaccy call/return call (sp ?1) (pc + 3) h , (sp ?2) (pc + 3) l , pc addr16, sp sp ?2 callf (sp ?1) (pc + 2) h , (sp ?2) (pc + 2) l , !addr11 2 5 pc 15-11 00001, pc 10-0 addr11, sp sp ?2 callt (sp ?1) (pc + 1) h , (sp ?2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ?2 brk (sp ?1) psw, (sp ?2) (pc + 1) h , 1 6 (sp ?3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp ?3, ie 0 ret pc h (sp + 1), pc l (sp), sp sp + 2 reti pc h (sp + 1), pc l (sp), 1 6 psw (sp + 2), sp sp + 3, r r r nmis 0 pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 psw 1 2 (sp ?1) psw, sp sp ?1 (sp ?1) rp h , (sp ?2) rp l , sp sp ?2 pop psw 1 2 psw (sp), sp sp + 1 r r r rp h (sp + 1), rp l (sp), sp sp + 2 movw sp, #word 4 10 sp word sp, ax 2 8 sp ax ax, sp 2 8 ax sp br !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 ax 2 8 pc h a, pc l x bc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 pc pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is accessed or an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to the internal rom program. 515 chapter 24 instruction set user? manual u12790ej2v0ud sfr.bit, $addr16 4 12 a.bit, $addr16 3 8 psw.bit, $addr16 4 12 [hl].bit, $addr16 3 10 12 b, $addr16 2 6 c, $addr16 2 6 saddr. $addr16 3 8 10 mnemonic operands bytes operation instruction group cpu control conditional branch clocks flag note 1 note 2 zaccy bt saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if(saddr.bit) = 1 sfr.bit, $addr16 4 11 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 9 pc pc + 3 + jdisp8 if psw.bit = 1 [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 1 bf saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if(saddr.bit) = 0 sfr.bit, $addr16 4 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 11 pc pc + 4 + jdisp8 if psw. bit = 0 [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 0 btclr saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if(saddr.bit) = 1 then reset(saddr.bit) pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit dbnz b b ?1, then pc pc + 2 + jdisp8 if b 0 c c ?, then pc pc + 2 + jdisp8 if c 0 (saddr) (saddr) ?1, then pc pc + 3 + jdisp8 if(saddr) 0 sel rbn 2 4 rbs1, 0 n nop 1 2 no operation ei 2 6 ie 1(enable interrupt) di 2 6 ie 0(disable interrupt) halt 2 6 set halt mode stop 2 6 set stop mode notes 1. when the internal high-speed ram area is accessed or an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to the internal rom program. 516 chapter 24 instruction set user? manual u12790ej2v0ud 24.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz 517 chapter 24 instruction set user? manual u12790ej2v0ud 2nd operand [hl + byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + b] $addr16 1 none 1st operand [hl + c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw note except r = a 518 chapter 24 instruction set user? manual u12790ej2v0ud (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand 1st operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr 2nd operand 1st operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 #word ax rp note sfrp saddrp !addr16 sp none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none 519 chapter 24 instruction set user? manual u12790ej2v0ud ax !addr16 !addr11 [addr5] $addr16 (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz 2nd operand 1st operand basic instruction br call callf callt br br bc bnc bz bnz compound bt instruction bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop 520 user? manual u12790ej2v0ud chapter 25 electrical specifications absolute maximum ratings (t a = 25 c) (notes are explained on the next page.) caution if the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. the absolute maximum ratings, therefore, are the values exceeding which the product may be physically damaged. be sure to use the product with these ratings never being exceeded. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. parameter symbol conditions rating unit supply voltage v dd ?.3 to +6.0 v v dd port ?.3 to v dd + 0.3 note 1 v av dd ?.3 to v dd + 0.3 note 1 v v dd pll ?.3 to v dd + 0.3 note 1 v v pp pd178f098 only, note 2 ?.3 to +10.5 v input voltage v i ?.3 to v dd + 0.3 v output voltage v o excluding p130 to p137 ?.3 to v dd + 0.3 v output breakdown v bds p130 to p137 n-ch open drain 16 v voltage analog input voltage v an p10 to p17 analog input pin ?.3 to v dd + 0.3 v high-level output i oh per pin ? ma current total of p00, p01, p20 to p27, p50 to p57, ?5 ma and p70 to p73 total of p02 to p07, p30 to p37, p40 to p47, ?5 ma p60 to p67, p74 to p77, and p120 to p124 total of p100 to p102 ?0 ma low-level output i ol note 3 per pin peak value 16 ma current r.m.s 8 ma total of p00, p01, p20 to p27, peak value 30 ma p50 to p57, and p70 to p73 r.m.s 15 ma total of p02 to p07, p30 to p37, peak value 30 ma p40 to p47, p60 to p67, p74 to p77, r.m.s 15 ma p120 to p124, and p130 to p137 total of p100 to 102 peak value 20 ma r.m.s 10 ma operating temperature t a during normal operation ?0 to +85 c during flash memory programming 10 to 40 c storage temperature t stg ?5 to +125 c 521 chapter 25 electrical specifications user? manual u12790ej2v0ud notes 1. keep the voltage at v dd port, av dd , and v dd pll the same as that at the v dd pin. 2. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. - when supply voltage rises v pp must exceed v dd 1 ms or more after v dd has reached the lower-limit value (3.5 v) of the operating voltage range (see a in the figure below). - when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (3.5 v) of the operating voltage range of v dd (see b in the figure below). 3. the rms value should be calculated as follows: [rms value] = [peak value] duty 3.5 v v dd 0 v 0 v v pp 3.5 v a b 522 chapter 25 electrical specifications user s manual u12790ej2v0ud recommended supply voltage ranges (t a = ?0 to +85 c) parameter symbol conditions min. typ. max. unit supply voltage v dd1 when cpu and pll are operating 4.5 5.0 5.5 v v dd2 when cpu is operating and pll is stopped 3.5 5.0 5.5 v data retention voltage v ddr when crystal oscillation stops 2.3 5.5 v output breakdown v bds p130 to p137 (n-ch open drain) 15 v voltage dc characteristics (t a = ?0 to +85 c, v dd = 3.5 to 5.5 v) (1/3) parameter symbol conditions min. typ. max. unit high-level input v ih1 p10 to p17, p21, p23, p30, p31, p36, p37, p40 to 0.7 v dd v dd v voltage p47, p50 to p57, p60 to p67, p71, p73, p75 to p77, p100 to p102, p120, p122 to p124 v ih2 p00 to p07, p20, p22, p24 to p27, p32 to p35, p70, 0.8 v dd v dd v p72, p74, p121, reset low-level input v il1 p10 to p17, p21, p23, p30, p31, p36, p37, p40 to 0 0.3 v dd v voltage p47, p50 to p57, p60 to p67, p71, p73, p75 to p77, p100 to p102, p120, p122 to p124 v il2 p00 to p07, p20, p22, p24 to p27, p32 to p35, p70, 0 0.2 v dd v p72, p74, p121, reset high-level output v oh1 4.5 v v dd 5.5 v, v dd 1.0 v voltage i oh = 1 ma 3.5 v v dd < 4.5 v, v dd 0.5 v i oh = 100 a v oh2 eo0, eo1 v dd = 4.5 to 5.5 v, v dd 1.0 v i oh = 3 ma low-level output v oh1 4.5 v v dd 5.5 v, 1.0 v voltage i ol = 1 ma 3.5 v v dd < 4.5 v, 0.5 v i ol = 100 a v ol2 eo0, eo1 v dd = 4.5 to 5.5 v, 1.0 v i ol = 3 ma high-level input i lih p00 to p07, p10 to p17, v i = v dd 3 a leakage current p20 to p24, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p100 to p102, p120 to p124, reset remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. p00 to p07, p20 to p24, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p100 to p102, p120 to p124 p00 to p07, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p100 to p102, p120 to p124, p130 to p137 523 chapter 25 electrical specifications user s manual u12790ej2v0ud parameter symbol conditions min. typ. max. unit low-level input i lil p00 to p07, p10 to p17, v i = 0 v 3 a current leakage p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p100 to p102, p120 to p124, reset i loh1 p130 to p137 v o = 15 v 3 a i lol1 p130 to p137 v o = 0 v 3 a i loh2 p25 to p27 v o = v dd 3 a (at n-ch open-drain i/o) i lol2 p25 to p27 v o = 0 v 3 a (at n-ch open-drain i/o) i loh3 eo0, eo1 v o = v dd 3 a i lol3 eo0, eo1 v o = 0 v 3 a dc characteristics (t a = ?0 to +85 c, v dd = 3.5 to 5.5 v) (2/3) output off current leakage 524 chapter 25 electrical specifications user s manual u12790ej2v0ud parameter symbol conditions min. typ. max. unit supply current note i dd1 fx = 4.5 mhz 2.5 15 ma ( pd178076, 178078) i dd2 fx = 6.3 mhz 4.0 20 ma ( pd178076, 178078, 178096a, 178098a) i dd3 fx = 4.5 mhz 0.2 0.8 ma ( pd178076, 178078) i dd4 fx = 6.3 mhz 0.3 1.0 ma ( pd178076, 178078, 178096a, 178098a) supply current note i dd1 fx = 4.5 mhz 5.0 18 ma ( pd178f098) i dd2 fx = 6.3 mhz 7.0 20 ma i dd3 fx = 4.5 mhz 0.3 0.8 ma i dd4 fx = 6.3 mhz 0.4 1.0 ma v ddr1 when crystal resonator is oscillating 3.5 5.5 v v ddr2 when crystal oscillation is power-failure detection 2.2 v stopped function v ddr3 data memory held 2.0 v data retention i ddr1 when crystal oscillation is t a = 25 c, 2.0 4.0 a current stopped v dd = 5 v i ddr2 t a = 40 to +85 c, 2.0 20 a v dd = 3.5 to 5.5 v dc characteristics (t a = ?0 to +85 c, v dd = 3.5 to 5.5 v) (3/3) note excluding av dd current and v dd pll current. remarks 1. f x : system clock oscillation frequency 2. unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. (mask rom versions) data retention voltage when cpu is operating and pll is stopped. sine wave input to x1 pin v i = v dd in halt mode with pll stopped. sine wave input to x1 pin v i = v dd when cpu is operating and pll is stopped. sine wave input to x1 pin v i = v dd in halt mode with pll stopped. sine wave input to x1 pin v i = v dd 525 chapter 25 electrical specifications user s manual u12790ej2v0ud reference characteristics (t a = ?0 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit supply current i dd5 when cpu and pll are operating. 5 ma sine wave input to vcoh pin f in = 160 mhz, v in = 0.15 v p-p ac characteristics (1) basic operation (t a = ?0 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol conditions min. typ. max. unit t cy f x = 6.3 mhz 0.32 5.08 s f x = 4.5 mhz note 1 0.44 7.11 s ti00, ti01 input t tih0 , 4/fsam note 2 s high-/low-level t til0 width ti50, ti51 input f ti5 2 mhz frequency ti50, ti51 input t tih5 , 200 ns high-/low-level t til5 width interrupt input t inth , intp0 to intp7 1 s high-/low-level t intl width reset pin t rsl 10 s low-level width notes 1. when the iebus controller of the pd178096a, 178098a, and 178f098 is used, the 4.5 mhz crystal resonator cannot be used. use the 6.3 mhz crystal resonator. 2. f sam = f x /2, f x /4, f x /64 selectable by bits 0 and 1 (prm00 and prm01) of prescaler mode register 0 (prm0). however, f sam = f x /8 when the valid edge of ti00 is selected as the count clock. cycle time (minimum instruction execution time) pd178f098 8 ma mask rom versions 526 chapter 25 electrical specifications user s manual u12790ej2v0ud (2) serial interface (t a = ?0 to +85 c, v dd = 3.5 to 5.5 v) (a) serial interface sio0 (i) 3-wire serial i/o mode (sck0 ... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy1 v dd = 4.5 to 5.5 v 800 ns v dd = 3.5 to 5.5 v 1600 ns sck0 high-/low-level width t kh1 ,v dd = 4.5 to 5.5 v t kcy1 /2 50 ns t kl1 v dd = 3.5 to 5.5 v t kcy1 /2 100 ns si0 setup time (to sck0 )t sik1 v dd = 4.5 to 5.5 v 100 ns v dd = 3.5 to 5.5 v 150 ns si0 hold time (from sck0 )t ksi1 400 ns so0 output delay time from sck0 t kso1 c = 100 pf note 300 ns note c is the load capacitance of the sck0 and so0 output lines. (ii) 3-wire serial i/o mode (sck0 ... external clock input) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy2 v dd = 4.5 to 5.5 v 800 ns v dd = 3.5 to 5.5 v 1600 ns sck0 high-/low-level width t kh2 ,v dd = 4.5 to 5.5 v 400 ns t kl2 v dd = 3.5 to 5.5 v 800 ns si0 setup time (to sck0 )t sik2 100 ns si0 hold time (from sck0 )t ksi2 400 ns so0 output delay time from sck0 t kso2 c = 100 pf note 300 ns sck0 rise, fall time t r2 , t f2 1000 ns note c is the load capacitance of the so0 output line. 527 chapter 25 electrical specifications user s manual u12790ej2v0ud (iii) sbi mode (sck0 ... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy3 v dd = 4.5 to 5.5 v 800 ns v dd = 3.5 to 5.5 v 3200 ns sck0 high-/low-level width t kh3 ,v dd = 4.5 to 5.5 v t kcy3 /2 50 ns t kl3 v dd = 3.5 to 5.5 v t kcy3 /2 150 ns sb0, sb1 setup time (to sck0 )t sik3 v dd = 4.5 to 5.5 v 100 ns v dd = 3.5 to 5.5 v 300 ns sb0, sb1 hold time (from sck0 ) t ksi3 t kcy3 /2 ns sb0, sb1 output delay time from t kso3 r = 1 k ? v dd = 4.5 to 5.5 v 0 250 ns sck0 c = 100 pf note v dd = 3.5 to 5.5 v 0 1000 ns sb0, sb1 from sck0 t ksb t kcy3 ns sck0 from sb0, sb1 t sbk t kcy3 ns sb0, sb1 high-level width t sbh t kcy3 ns sb0, sb1 low-level width t sbl t kcy3 ns note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. (iv) sbi mode (sck0 ... external clock input) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy4 v dd = 4.5 to 5.5 v 800 ns v dd = 3.5 to 5.5 v 3200 ns sck0 high-/low-level width t kh4 ,v dd = 4.5 to 5.5 v 400 ns t kl4 v dd = 3.5 to 5.5 v 1600 ns sb0, sb1 setup time (to sck0 )t sik4 v dd = 4.5 to 5.5 v 100 ns v dd = 3.5 to 5.5 v 300 ns sb0, sb1 hold time (from sck0 ) t ksi4 t kcy4 /2 ns sb0, sb1 output delay time from t kso4 r = 1 k ? v dd = 4.5 to 5.5 v 0 250 ns sck0 c = 100 pf note v dd = 3.5 to 5.5 v 0 1000 ns sb0, sb1 from sck0 t ksb t kcy4 ns sck0 from sb0, sb1 t sbk t kcy4 ns sb0, sb1 high-level width t sbh t kcy4 ns sb0, sb1 low-level width t sbl t kcy4 ns sck0 rise, fall time t r4 , t f4 1000 ns note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines. 528 chapter 25 electrical specifications user s manual u12790ej2v0ud (v) 2-wire serial i/o mode (sck0 ... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy5 r = 1 k ? 1600 ns sck0 high-level width t kh5 c = 100 pf note t kcy5 /2 160 ns sck0 low-level width t kl5 v dd = 4.5 to 5.5 v t kcy5 /2 50 ns v dd = 3.5 to 5.5 v t kcy5 /2 100 ns sb0, sb1 setup time (to sck0 )t sik5 v dd = 4.5 to 5.5 v 300 ns v dd = 3.5 to 5.5 v 350 ns sb0, sb1 hold time (from sck0 ) t ksi5 600 ns sb0, sb1 output delay time from t kso5 0 300 ns sck0 note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. (vi) 2-wire serial i/o mode (sck0 ... external clock input) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy6 1600 ns sck0 high-level width t kh6 650 ns sck0 low-level width t kl6 800 ns sb0, sb1 setup time (to sck0 )t sik6 100 ns sb0, sb1 hold time (from sck0 ) t ksi6 t kcy6 /2 ns sb0, sb1 output delay time from t kso6 r = 1 k ? v dd = 4.5 to 5.5 v 0 300 ns sck0 c = 100 pf note v dd = 3.5 to 5.5 v 0 500 ns sck0 rise, fall time t r6 , t f6 1000 ns note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines. 529 chapter 25 electrical specifications user s manual u12790ej2v0ud parameter symbol conditions min. typ. max. unit scl cycle time t kcy7 r = 1 k ? 10 s scl high-level width t kh7 c = 100 pf note t kcy7 160 ns scl low-level width t kl7 t kcy7 50 ns sda0, sda1 setup time (to scl ) t sik7 200 ns sda0, sda1 hold time t ksi7 0ns (from scl ) sda0, sda1 output delay time t kso7 v dd = 4.5 to 5.5 v 0 300 ns (from scl ) v dd = 3.5 to 5.5 v 0 500 ns sda0, sda1 from scl or t ksb 200 ns sda0, sda1 from scl scl from sda0, sda1 t sbk 400 ns sda0, sda1 high-level width t sbh 500 ns (vii) i 2 c bus mode (scl ... internal clock output) note r and c are the load resistance and load capacitance of scl, sda0 and sda1 output line. (viii) i 2 c bus mode (scl ... external clock input) parameter symbol conditions min. typ. max. unit scl cycle time t kcy8 1000 ns scl high-/low-level width t kh8, t kl8 400 ns sda0, sda1 setup time (to scl ) t sik8 200 ns sda0, sda1 hold time t ksi8 0ns (from scl ) sda0, sda1 output delay time t kso8 r = 1 k ? v dd = 4.5 to 5.5 v 0 300 ns from scl c = 100 pf note v dd = 3.5 to 5.5 v 0 500 ns sda0, sda1 from scl or t ksb 200 ns sda0, sda1 from scl scl from sda0, sda1 t sbk 400 ns sda0, sda1 high-level width t sbh 500 ns scl rise, fall time t r8 , t f8 1000 ns note r and c are the load resistance and load capacitance of the sda0 and sda1 output lines. 530 chapter 25 electrical specifications user s manual u12790ej2v0ud note c is the load capacitance of the sck1 and so1 output lines. (ii) 3-wire serial i/o mode (sck1 ... external clock input) (b) serial interface sio1 (i) 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy9 800 ns sck1 high/low-level width t kh9 , t kcy9 /2 50 ns t kl9 si1 setup time (to sck1 )t sik9 100 ns si1 hold time (from sck1 )t ksi9 400 ns so1 output delay time (from sck1 ) t kso9 c = 100 pf note 300 ns parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy10 800 ns sck1 high/low-level width t kh10 , 400 ns t kl10 si1 setup time (to sck1 )t sik10 100 ns si1 hold time (from sck1 )t ksi10 400 ns so1 output delay time (from sck1 )t kso10 c = 100 pf note 300 ns sck1 rise, fall time t r10 , t f10 1000 ns note c is the load capacitance of the so1 output line. 531 chapter 25 electrical specifications user s manual u12790ej2v0ud (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1 ... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy11 800 ns sck1 high/low-level width t kh11 , t kcy11 /2 50 ns t kl11 si1 setup time (to sck1 )t sik11 100 ns si1 hold time (from sck1 )t ksi11 400 ns so1 output delay time (from sck1 )t kso11 c = 100 pf note 300 ns stb from sck1 t sbd t kcy11 /2 100 t kcy11 /2 + 100 ns strobe signal high-level width t sbw t kcy11 /2 30 t kcy11 /2 + 30 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 100 ns (from busy signal detection timing) sck1 from busy inactive t sps 200 ns note c is the load capacitance of the so1 output line. (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1 ... external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy12 800 ns sck1 high/low-level width t kh12 , 400 ns t kl12 si1 setup time (to sck1 )t sik12 100 ns si1 hold time (from sck1 )t ksi12 400 ns so1 output delay time (from sck1 )t kso12 c = 100 pf note 300 ns sck1 rise, fall time t r12 , t f12 1000 ns note c is the load capacitance of the so1 output line. 532 chapter 25 electrical specifications user s manual u12790ej2v0ud note c is the load capacitance of the sck3 and so3 output lines. (ii) 3-wire serial i/o mode (sck3 ... external clock input) (c) serial interface sio3 (i) 3-wire serial i/o mode (sck3 ... internal clock output) parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy13 800 ns sck3 high/low-level width t kh13 , t kcy13 /2 50 ns t kl13 si3 setup time (to sck3 )t sik13 100 ns si3 hold time (from sck3 )t ksi13 400 ns so3 output delay time (from sck3 ) t kso13 c = 100 pf note 300 ns parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy14 800 ns sck3 high/low-level width t kh14 , 400 ns t kl14 si3 setup time (to sck3 )t sik14 100 ns si3 hold time (from sck3 )t ksi14 400 ns so3 output delay time (from sck3 )t kso14 c = 100 pf note 300 ns sck3 rise, fall time t r14 , t f14 1000 ns note c is the load capacitance of the so3 output line. (d) serial interface uart0 (dedicated baud rate generator output) note parameter symbol conditions min. typ. max. unit transfer rate 38400 bps note pd178076, 178078, and 178f098 only. 533 chapter 25 electrical specifications user s manual u12790ej2v0ud ac timing test points (excluding x1 input) ti timing t til0 t tih0 ti00, ti01 1/f ti5 t til5 t tih5 ti50,ti51 interrupt input timing t intl t inth intp0 to intp7 reset input timing t rsl reset 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points 534 chapter 25 electrical specifications user s manual u12790ej2v0ud serial transfer timing 3-wire serial i/o mode: remark m = 1, 2, 9, 10, 13, 14 n = 2, 10, 14 sbi mode (bus release signal transfer): t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t sbl t sbh t ksb t sbk t ksi3, 4 t kso3, 4 sb0, sb1 t r4 t f4 t kcym t klm t khm sck0, sck1, sck3 si0, si1, si3 so0, so1, so3 t sikm t ksim t ksom input data output data t rn t fn 535 chapter 25 electrical specifications user s manual u12790ej2v0ud sbi mode (command signal transfer): t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t ksb t sbk t ksi3, 4 t kso3, 4 sb0, sb1 t r4 t f4 2-wire serial i/o mode: t kso5, 6 t sik5, 6 t kcy5, 6 t kl5, 6 t kh5, 6 sck0 t ksi5, 6 sb0, sb1 t f6 t r6 i 2 c bus mode: scl sda0, sda1 t sbh t kl7, 8 t sbk t f8 t r8 t kcy7, 8 t ksi7, 8 t kh7, 8 t sik7, 8 t kso7, 8 t sbk t ksb t ksb 536 chapter 25 electrical specifications user s manual u12790ej2v0ud 3-wire serial i/o mode with automatic transmit/receive function: t sbw t sbd t kcy11 , 12 t kh11 , 12 t ksi11 , 12 t kso11 , 12 t sik11 , 12 d2 d1 d0 d7 d7 d2 d1 d0 so1 si1 sck1 stb t r12 t kl11 , 12 t f12 3-wire serial i/o mode with automatic transmit/receive function (busy processing): t bys sck1 t sps busy (active high) 789 note 10 note 10 + n note 1 t byh note the signal is not actually driven low here; it is shown as such to indicate the timing. iebus controller characteristics note 1 (t a = 40 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol conditions min. typ. max. unit iebus system f s fixed to mode 1 6.3 note 2 mhz clock frequency notes 1. pd178096a, 178098a, only 178f098 only. 2. although the system clock frequency is 6.0 mhz in the iebus standard, in these products, normal operation is guaranteed at 6.3 mhz. remark 6.0 mhz and 6.3 mhz cannot both be used as the iebus system clock frequency. 537 chapter 25 electrical specifications user s manual u12790ej2v0ud operating frequency a/d converter characteristics (t a = 40 to +85 c, v dd = av dd = 3.5 to 5.5 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit v dd = 4.5 to 5.5 v 1.0 %fsr v dd = 3.5 to 5.5 v 1.4 %fsr conversion time t conv 15.2 45.7 s analog input voltage v ian 0v dd v notes 1. excluding quantization error ( 0.2%fsr) 2. this value is indicated as a ratio to the full-scale value. pll characteristics (t a = 40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit f in1 vcol pin, mf mode, sine wave input, v in = 0.15 v p-p 0.5 3.0 mhz f in2 vcol pin, hf mode, sine wave input, v in = 0.15 v p-p 10 40 mhz f in3 vcoh pin, vhf mode, sine wave input, v in = 0.15 v p-p 60 130 mhz f in4 vcoh pin, vhf mode, sine wave input, v in = 0.3 v p-p 40 160 mhz remark the above values are the result of evaluation of the device by nec electronics. if the device is likely to be affected by noise in your application, it is recommended to use the device at an amplitude voltage higher than the above values. ifc characteristics (t a = 40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit operating f in5 amifc pin, amif count mode, sine wave input, 0.4 0.5 mhz frequency v in = 0.15 v p-p f in6 fmifc pin, fmif count mode, sine wave input, 10 11 mhz v in = 0.15 v p-p f in7 fmifc pin, amif count mode, sine wave input, 0.4 0.5 mhz v in = 0.15 v p-p remark the above values are the result of evaluation of the device by nec electronics. if the device is likely to be affected by noise in your application, it is recommended to use the device at an amplitude voltage higher than the above values. total conversion error notes 1, 2 538 chapter 25 electrical specifications user s manual u12790ej2v0ud flash memory programming characteristics (t a = 10 to 40 c, v dd = 3.5 to 5.5 v) (1) write/erase characteristics parameter symbol conditions min. typ. max. unit write current (v dd pin) note i ddw when v pp = v pp1 , f x = 6.3 mhz 23 ma write current (v pp pin) note i ppw when v pp = v pp1 , f x = 6.3 mhz 20 ma erase current (v dd pin) note i dde when v pp = v pp1 , f x = 6.3 mhz 23 ma erase current (v pp pin) note i ppe when v pp = v pp1 100 ma unit erase time t er 0.5 1 1 s total erase time t era 20 s number of rewrites c wrt erase and write are counted as one cycle 20 times v pp power supply voltage v pp0 in normal mode 0 0.2 v dd v v pp1 during flash memory programming 9.7 10.0 10.3 v note av dd current and port current (current flowing to internal pull-up resistors) are not included. remark f x : system clock oscillation frequency (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit v pp setup time t psron v pp high voltage 1.0 s v pp setup time from v dd t drpsr v pp high voltage 10 s reset setup time from v pp t psrrf v pp high voltage 1.0 s v pp count start time from reset t rfcf 1.0 s count execution time t count 2.0 ms v pp counter high-level width t ch 8.0 s v pp counter low-level width t cl 8.0 s v pp counter noise elimination width t nfw 40 ns flash write mode setting timing v dd v dd 0 v v dd reset (input) 0 v v pph v ppl v pp v pp t rfcf t psron t psrrf t drpsr t ch t cl t count 539 user? manual u12790ej2v0ud chapter 26 package drawing 80 81 50 100 1 31 30 51 100-pin plastic qfp (14x20) hi j detail of lead end m q r k m l p s s n g f note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 23.6 0.4 20.0 0.2 0.30 0.10 0.6 h 17.6 0.4 i c 14.0 0.2 0.15 j 0.65 (t.p.) k 1.8 0.2 l 0.8 0.2 f 0.8 p100gf-65-3ba1-4 n p q 0.10 2.7 0.1 0.1 0.1 r5 5 s 3.0 max. m 0.15 + 0.10 ? 0.05 c d a b s 540 user? manual u12790ej2v0ud chapter 27 recommended soldering conditions the pd178078, 178098a subseries should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) table 27-1. soldering conditions for surface-mount type pd178076gf-xxx-3ba: 100-pin plastic qfp (14 20) pd178078gf-xxx-3ba: 100-pin plastic qfp (14 20) pd178096agf-xxx-3ba: 100-pin plastic qfp (14 20) pd178098agf-xxx-3ba: 100-pin plastic qfp (14 20) pd178f098gf-3ba: 100-pin plastic qfp (14 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-3 (210 c min.), number of times: 3 max. vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-3 (200 c min.), number of times: 3 max. wave soldering solder bath temperature: 260 c max., time: 10 seconds max., ws60-00-1 number of times: 1, preheating temperature: 120 c max., (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per device side) caution do not use two or more soldering methods together (except partial heating). 541 user? manual u12790ej2v0ud appendix a development tools the following development tools are available for the development of systems which employ the pd178078, 178098a subseries. figure a-1 shows a configuration example of the tools. support for pc98-nx series unless otherwise specified, products supported by ibm pc/at tm compatible machines can be used for pc98- nx series computers. when using pc98-nx series computers, refer to the description for ibm pc/at compatible machines. windows unless otherwise specified, ?indows?means the following oss. windows 3.1 windows 95 windows 98 windows 2000 windows nt tm ver. 4.0 542 appendix a development tools user? manual u12790ej2v0ud figure a-1. configuration of development tools notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is only used for windows. language processing software assembler package c compiler package device file c library source file note 1 debugging software integrated debugger system simulator host machine (pc or ews) interface adapter, pc card interface, etc. in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory write adapter flash memory software package project manager (windows only) note 2 software package flash memory write environment control software embedded software real-time os i/o board performance board power supply unit 543 appendix a development tools user s manual u12790ej2v0ud a.1 software package sp78k0 this package contains various software tools for 78k/0 series development. software package the following tools are included. ra78k0, cc78k0, id78k0-ns, sm78k0, and various device files part number: s sp78k0 remark in the part number differs depending on the os used. s sp78k0 host machine os supply medium ab17 windows (japanese version) cd-rom bb17 windows (english version) a.2 language processing software ra78k0 assembler package cc78k0 c compiler package df178098 note 1 device file cc78k0-l note 2 c library source file notes 1. the df178098 can be used in common with the ra78k0, cc78k0, sm78k0, id78k0-ns, id78k0, and rx78k0. 2. cc78k0-l is not included in the software package (sp78k0). this assembler converts programs written in mnemonics into object codes executable with a microcontroller. further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with a device file (df178098) (sold separately). 544 appendix a development tools user s manual u12790ej2v0ud remark in the part number differs depending on the host machine and os used. s ra78k0 s cc78k0 host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at and compatibles windows (english version) ab17 windows (japanese version) cd-rom bb17 windows (english version) 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) s df178098 s cc78k0-l host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at and compatibles windows (english version) 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 sparcstation sunos (rel. 4.1.4), 3.5-inch 2hd fd 3k15 solaris (rel. 2.5.1) 1/4-inch cgmt a.3 control software project manager this is control software designed to enable efficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. 545 appendix a development tools user s manual u12790ej2v0ud a.5 debugging tools (hardware) a.5.1 when using in-circuit emulator ie-78k0-ns, ie-78k0-ns-a ie-78k0-ns in-circuit emulator ie-78k0-ns-pa performance board ie-78k0-ns-a in-circuit emulator ie-70000-mc-ps-b power supply unit ie-70000-98-if-c interface adapter ie-70000-cd-if-a pc card interface ie-70000-pc-if-c interface adapter ie-70000-pci-if-a interface adapter ie-178098-ns-em1 emulation board np-100gf-tq np-h100gf-tq emulation probe tgf-100rbp conversion adapter np-100gf emulation probe ev-9200gf-100 conversion socket (see figures a-2 and a-3) remarks 1. np-100gf, np-100gf-tq, and np-h100gf-tq are products of naito densei machida mfg. co., ltd. contact: +81-45-475-4191 naito densei machida mfg. co., ltd. 2. tgf-100rbp is a product of tokyo eletech corporation. inquiry: daimaru kogyo, ltd. phone: tokyo +81-3-3820-7112 electronics dept. osaka +81-6-6244-6672 electronics 2nd dept. 3. the ev-9200gf-100 is sold in sets of 5 units. the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it is used with an integrated debugger (id78k0-ns). this emulator should be used in combination with a power supply unit, emulation probe, and interface adapter, which is required to connect this emulator to the host machine. this board is used for extending the ie-78k0-ns functions, and is used connected to the ie-78k0-ns. with the addition of this board, the addition of a coverage function, enhancement of tracer and timer functions, and other such debugging function enhancements are possible. in-circuit emulator that combines the ie-78k0-ns and ie-78k0-ns-pa this adapter is used for supplying power from a 100 to 240 v ac output. this adapter is required when using a pc-9800 series computer (except notebook type) as the ie-78k0-ns host machine (c bus compatible). this is pc card and interface cable required when using a notebook-type computer as the ie-78k0-ns host machine (pcmcia socket compatible). this adapter is required when using an ibm pc/at compatible computer as the ie-78k0- ns host machine (isa bus compatible). this adapter is required when using a pc with a pci bus as the ie-78k0-ns host machine. this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. this probe is used to connect the in-circuit emulator to the target system and is designed for a 100-pin plastic qfp (gf-3ba type). it should be used in combination with the tgf- 100rbp. this conversion socket connects the np-100gf-tq or np-h100gf-tq to the target system board designed to mount a 100-pin plastic qfp (gf-3ba type). this probe is for a 100-pin plastic qfp (gf-3ba type) and connects an in-circuit emulator and the target system. this conversion socket connects the board of a target system created to mount a 100-pin plastic qfp (gf-3ba type) and np-100gf. 546 appendix a development tools user? manual u12790ej2v0ud a.5.2 when using in-circuit emulator ie-78001-r-a ie-78001-r-a in-circuit emulator ie-70000-98-if-c interface adapter ie-70000-pc-if-c interface adapter ie-178098-ns-em1 emulation board ie-78k0-r-ex1 emulation probe conversion board ep-78064gf-r emulation probe ev-9200gf-100 conversion socket (see figures a-2 and a-3) remark the ev-9200gf-100 is sold in sets of five units. this is an in-circuit emulator for debugging the hardware and software when an application system using the 78k/0 series is developed. it is used with an integrated debugger (id78k0). this emulator is used with an emulation probe and interface adapter for connecting a host machine. this adapter is necessary when a pc-9800 series pc (except notebook type) is used as the host machine for the ie-78001-r-a (c bus compatible). this adapter is necessary when an ibm pc/at or compatible machine is used as the host machine for the ie-78001-r-a (isa bus compatible). this board is used with an in-circuit emulator and emulation probe conversion board to emulate device-specific peripheral hardware. this board is necessary for using the ie-178098-ns-em1 on the ie-78001-r-a. this probe is for an 100-pin plastic qfp (gf-3ba type) and connects an in-circuit emulator and the target system. this conversion socket connects the board of a target system created to mount an 100-pin plastic qfp (gf-3ba type) and ep-78064gf-r. 547 appendix a development tools user s manual u12790ej2v0ud a.6 debugging tools (software) sm78k0 this is a system simulator for the 78k/0 series. the sm78k0 is windows-based system simulator software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of the sm78k0 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. the sm78k0 should be used in combination with a device file (df178098) (sold separately). part number: s sm78k0 id78k0-ns this debugger supports the in-circuit emulators for the 78k/0 series. the integrated debugger id78k0-ns is windows-based software. (supporting in-circuit emulators it has improved c-compatible debugging functions and can display the results of ie-78k0-ns and ie-78k0-ns-a) tracing with the source program using an integrating window function that associates id78k0 the source program, disassemble display, and memory display with the trace result. integrated debugger it should be used in combination with a device file (sold separately). (supporting in-circuit emulator part number: s id78k0-ns ie-78001-r-a) s id78k0 remark in the part number differs depending on the host machine and os used. s sm78k0 s id78k0-ns s id78k0 host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at and compatibles windows (english version) ab17 windows (japanese version) cd-rom bb17 windows (english version) 548 appendix a development tools user s manual u12790ej2v0ud a.7 embedded software rx78k0 the rx78k0 is a real-time os conforming to the itron specifications. real-time os a tool (configurator) for generating the nucleus of the rx78k0 and multiple information tables is supplied. used in combination with an assembler package (ra78k0) and device file (df178098) (both sold separately). 549 appendix a development tools user s manual u12790ej2v0ud a.8 upgrading old version of in-circuit emulator for 78k/0 series to ie-78001-r-a if you already have an old type of in-circuit emulator for the 78k/0 series (ie-78000-r or ie-78000-r-a), it can be upgraded to have equivalent functions to the ie-78001-r-a by exchanging the break board with the ie-78001-r-bk. table a-1. upgrading old version of in-circuit emulator for 78k/0 series to ie-78001-r-a your in-circuit emulator upgrading of housing note necessary board ie-78000-r necessary ie-78001-r-bk ie-78000-r-a not necessary note to upgrade the housing, your in-circuit emulator must be brought to nec electronics. 550 appendix a development tools user s manual u12790ej2v0ud a.9 drawing for conversion socket (ev-9200gf-100) package and recommended board mounting pattern figure a-2. ev-9200gf-100 package drawing (for reference only) ev-9200gf-100 a d e b f 1 no.1 pin index m n o l k s r q i h g p c j ev-9200gf-100-g0e item millimeters inches a b c d e f g h i j k l m n o p q r s 24.6 21 15 18.6 4-c 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.969 0.827 0.591 0.732 4-c 0.079 0.031 0.472 0.89 0.996 0.236 0.654 076 0.323 0.315 0.098 0.079 0.014 0.091 0.059 551 appendix a development tools user s manual u12790ej2v0ud figure a-3. ev-9200gf-100 recommended board mounting pattern (for reference only) f h e d a b c i j k l 0.026 1.142=0.742 0.026 0.748=0.486 ev-9200gf-100-p1e item millimeters inches a b c d e f g h i j k l 26.3 21.6 15.6 20.3 12 0.05 6 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 1.035 0.85 0.614 0.799 0.472 0.236 0.014 0.093 0.091 0.062 0.65 0.02 29=18.85 0.05 0.65 0.02 19=12.35 0.05 +0.001 ?.002 +0.002 ?.002 +0.001 ?.002 +0.003 ?.002 +0.003 ?.002 +0.003 ?.002 +0.001 ?.001 +0.001 ?.002 +0.001 ?.002 g based on ev-9200gf-100 (2) pad drawing (in mm) the dimensions of the mount pad for ev-9200 and that for target device (qfp) may differ in some parts. for the recommended mount pad dimensions for qfp, refer to the "semiconductor device mount manual" website (http://www.necel.com/pkg/en/mount/index.html) . caution 552 user? manual u12790ej2v0ud appendix b register index b.1 register index (register name) 16-bit capture/compare register 00 (cr00) ............................................................................................. 121 16-bit capture/compare register 01 (cr01) ............................................................................................. 122 16-bit timer counter 0 (tm0) ..................................................................................................................... 121 16-bit timer mode control register 0 (tmc0) ........................................................................................... 124 16-bit timer output control register 0 (toc0) .......................................................................................... 127 8-bit compare register 50 (cr50) ............................................................................................................ 164 8-bit compare register 51 (cr51) ............................................................................................................ 164 8-bit timer counter 50 (tm50) ................................................................................................................... 163 8-bit timer counter 51 (tm51) ................................................................................................................... 163 8-bit timer mode control register 50 (tmc50) ......................................................................................... 166 8-bit timer mode control register 51 (tmc51) ......................................................................................... 166 [a] a/d conversion result register 3 (adcr3) ............................................................................................... 200 a/d converter mode register 3 (adm3) ................................................................................................... 201 analog input channel specification register 3 (ads3) ............................................................................ 203 asynchronous serial interface mode register 0 (asim0) ........................................................................ 351 asynchronous serial interface status register 0 (asis0) ........................................................................ 353 automatic data transmit/receive address pointer (adtp) ....................................................................... 298 automatic data transmit/receive control register (adtc) ....................................................................... 301 automatic data transmit/receive interval specification register (adti) .................................................. 303 [b] baud rate generator control register 0 (brgc0) .................................................................................... 353 beep frequency select register 0 (beepcl0) ........................................................................................ 195 [c] capture/compare control register 0 (crc0) ............................................................................................ 126 clock output select register (cks) ........................................................................................................... 196 [d] dts system clock select register (dtsck) ............................................................................................. 110 [e] external interrupt falling edge select flag (egn) ..................................................................................... 436 external interrupt rising edge select flag (egp) ...................................................................................... 436 [i] iebus communication successful counter (scr) .................................................................................... 405 iebus control data register (cdr) ........................................................................................................... 391 iebus control register 0 (bcr0) ............................................................................................................... 387 iebus data register (dr) .......................................................................................................................... 395 appendix b register index 553 user? manual u12790ej2v0ud iebus interrupt status register (isr) ........................................................................................................ 399 iebus partner address register (par) ..................................................................................................... 390 iebus slave address register (sar) ........................................................................................................ 390 iebus slave status register (ssr) ............................................................................................................ 404 iebus telegraph length register (dlr) ..................................................................................................... 394 iebus transmission counter (ccr) .......................................................................................................... 405 iebus unit address register (uar) ........................................................................................................... 390 iebus unit status register (usr) .............................................................................................................. 396 if counter control register (ifccr) ......................................................................................................... 470 if counter gate judge register (ifcjg) .................................................................................................... 470 if counter mode select register (ifcmd) ................................................................................................ 469 if counter register (ifcr) ........................................................................................................................ 223 internal extension ram size select register (ixs) .................................................................................. 495 interrupt mask flag register 0h (mk0h) ................................................................................................... 434 interrupt mask flag register 0l (mk0l) .................................................................................................... 434 interrupt mask flag register 1l (mk1l) .................................................................................................... 434 interrupt request flag register 0h (if0h) ................................................................................................. 433 interrupt request flag register 0l (if0l) ................................................................................................... 433 interrupt request flag register 1l (if1l) ................................................................................................... 433 interrupt timing specification register 0 (sint0) ...................................................................................... 232 [m] memory size select register (ims) ........................................................................................................... 494 [o] oscillation stabilization time select register (osts) ............................................................................... 113 [p] pll data register (pllr) .......................................................................................................................... 452 pll data register 0 (pllr0) .................................................................................................................... 452 pll data register h (pllrh) ................................................................................................................... 452 pll data register l (pllrl) .................................................................................................................... 452 pll data transfer register (pllns) ......................................................................................................... 456 pll mode select register (pllmd) .......................................................................................................... 453 pll reference mode register (pllrf) ..................................................................................................... 454 pll unlock f/f judge register 0 (pllul) ................................................................................................ 455 poc status register (pocs) .................................................................................................................... 491 port 0 (p0) ............................................................................................................................... ................ 91 port 1 (p1) ............................................................................................................................... ................ 92 port 2 (p2) ............................................................................................................................... ................ 93 port 3 (p3) ............................................................................................................................... ................ 95 port 4 (p4) ............................................................................................................................... ................ 96 port 5 (p5) ............................................................................................................................... ................ 97 port 6 (p6) ............................................................................................................................... ................ 98 port 7 (p7) ............................................................................................................................... ................ 99 port 10 (p10) ............................................................................................................................... .............. 101 port 12 (p12) ............................................................................................................................... .............. 103 port 13 (p13) ............................................................................................................................... .............. 105 appendix b register index 554 user? manual u12790ej2v0ud port mode register 0 (pm0) ...................................................................................................................... 106 port mode register 2 (pm2) ...................................................................................................................... 106 port mode register 3 (pm3) ...................................................................................................................... 106 port mode register 4 (pm4) ...................................................................................................................... 106 port mode register 5 (pm5) ...................................................................................................................... 106 port mode register 6 (pm6) ...................................................................................................................... 106 port mode register 7 (pm7) ...................................................................................................................... 106 port mode register 10 (pm10) .................................................................................................................. 106 port mode register 12 (pm12) .................................................................................................................. 106 power-fail compare mode register 3 (pfm3) .......................................................................................... 204 power-fail compare threshold value register 3 (pft3) ........................................................................... 200 prescaler mode register 0 (prm0) .......................................................................................................... 128 priority specification flag register 0h (pr0h) .......................................................................................... 435 priority specification flag register 0l (pr0l) ........................................................................................... 435 priority specification flag register 1l (pr1l) ........................................................................................... 435 processor clock control register (pcc) ................................................................................................... 112 [r] receive buffer register 0 (rxb0) ............................................................................................................. 349 [s] serial bus interface control register 0 (sbic0) ........................................................................................ 229 serial i/o shift register 0 (sio0) ............................................................................................................... 223 serial i/o shift register 1 (sio1) ............................................................................................................... 298 serial i/o shift register 3 (sio3) ............................................................................................................... 340 serial interface clock select register 0 (scl0) ........................................................................................ 226 serial operating mode register 0 (csim0) ............................................................................................... 227 serial operating mode register 1 (csim1) ............................................................................................... 299 serial operating mode register 3 (csim3) ............................................................................................... 341 slave address register 0 (sva0) .............................................................................................................. 223 [t] timer clock select register 50 (tcl50) .................................................................................................... 165 timer clock select register 51 (tcl51) .................................................................................................... 165 transmit shift register 0 (txs0) ............................................................................................................... 349 [v] vm45 control register (vm45c) ................................................................................................................ 492 [w] watchdog timer clock select register (wdcs) ........................................................................................ 190 watchdog timer mode register (wdtm) .................................................................................................. 191 appendix b register index 555 user? manual u12790ej2v0ud b.2 register index (symbol) [a] adcr3: a/d conversion result register 3 ............................................................................................ 200 adm3: a/d converter mode register 3 .............................................................................................. 201 ads3: analog input channel specification register 3 ....................................................................... 203 adtc: automatic data transmit/receive control register .................................................................. 301 adti: automatic data transmit/receive interval specification register ............................................ 303 adtp: automatic data transmit/receive address pointer ................................................................. 298 asim0: asynchronous serial interface mode register 0 .................................................................... 351 asis0: asynchronous serial interface status register 0 .................................................................... 353 [b] bcr0: iebus control register 0 ......................................................................................................... 387 beepcl0: beep frequency select register 0 .......................................................................................... 195 brgc0: baud rate generator control register 0 .................................................................................. 353 [c] ccr: iebus transmission counter ................................................................................................... 405 cdr: iebus control data register .................................................................................................... 391 cks: clock output select register ................................................................................................... 196 cr00: 16-bit capture/compare register 00 ....................................................................................... 121 cr01: 16-bit capture/compare register 01 ....................................................................................... 122 cr50: 8-bit compare register 50 ....................................................................................................... 164 cr51: 8-bit compare register 51 ....................................................................................................... 164 crc0: capture/compare control register 0 ....................................................................................... 126 csim0: serial operating mode register 0 ........................................................................................... 227 csim1: serial operating mode register 1 ........................................................................................... 299 csim3: serial operating mode register 3 ........................................................................................... 341 [d] dlr: iebus telegraph length register ............................................................................................. 394 dr: iebus data register ................................................................................................................. 395 dtsck: dts system clock select register .......................................................................................... 110 [e] egn: external interrupt falling edge select flag .............................................................................. 436 egp: external interrupt rising edge select flag .............................................................................. 436 [i] if0h: interrupt request flag register 0h .......................................................................................... 433 if0l: interrupt request flag register 0l ........................................................................................... 433 if1l: interrupt request flag register 1l ........................................................................................... 433 ifccr: if counter control register ...................................................................................................... 470 ifcjg: if counter gate judge register ............................................................................................... 470 ifcmd: if counter mode select register ............................................................................................. 469 ifcr: if counter register .................................................................................................................. 223 ims: memory size select register ................................................................................................... 494 appendix b register index 556 user? manual u12790ej2v0ud isr: iebus interrupt status register ............................................................................................... 399 ixs: internal extension ram size select register ......................................................................... 495 [m] mk0h: interrupt mask flag register 0h .............................................................................................. 434 mk0l: interrupt mask flag register 0l ............................................................................................... 434 mk1l: interrupt mask flag register 1l ............................................................................................... 434 [o] osts: oscillation stabilization time select register .......................................................................... 113 [p] p0: port 0 ............................................................................................................................... ....... 91 p1: port 1 ............................................................................................................................... ....... 92 p2: port 2 ............................................................................................................................... ....... 93 p3: port 3 ............................................................................................................................... ....... 95 p4: port 4 ............................................................................................................................... ....... 96 p5: port 5 ............................................................................................................................... ....... 97 p6: port 6 ............................................................................................................................... ....... 98 p7: port 7 ............................................................................................................................... ....... 99 p10: port 10 ............................................................................................................................... ..... 101 p12: port 12 ............................................................................................................................... ..... 103 p13: port 13 ............................................................................................................................... ..... 105 par: iebus partner address register .............................................................................................. 390 pcc: processor clock control register ............................................................................................ 112 pfm3: power-fail compare mode register 3 ..................................................................................... 204 pft3: power-fail compare threshold value register 3 ..................................................................... 200 pllmd: pll mode select register ....................................................................................................... 453 pllns: pll data transfer register ...................................................................................................... 456 pllr: pll data register .................................................................................................................... 452 pllr0: pll data register 0 ................................................................................................................. 452 pllrf: pll reference mode register ................................................................................................. 454 pllrh: pll data register h ................................................................................................................ 452 pllrl: pll data register l ................................................................................................................. 452 pllul: pll unlock f/f judge register 0 ............................................................................................ 455 pm0: port mode register 0 .............................................................................................................. 106 pm2: port mode register 2 .............................................................................................................. 106 pm3: port mode register 3 .............................................................................................................. 106 pm4: port mode register 4 .............................................................................................................. 106 pm5: port mode register 5 .............................................................................................................. 106 pm6: port mode register 6 .............................................................................................................. 106 pm7: port mode register 7 .............................................................................................................. 106 pm10: port mode register 10 ............................................................................................................ 106 pm12: port mode register 12 ............................................................................................................ 106 pocs: poc status register ................................................................................................................ 491 pr0h: priority specification flag register 0h ..................................................................................... 435 pr0l: priority specification flag register 0l ..................................................................................... 435 pr1l: priority specification flag register 1l ..................................................................................... 435 prm0: prescaler mode register 0 ...................................................................................................... 128 appendix b register index 557 user? manual u12790ej2v0ud [r] rxb0 receive buffer register 0 ........................................................................................................ 349 [s] sar: iebus slave address register ................................................................................................. 390 sbic0: serial bus interface control register 0 ................................................................................... 229 scl0: serial interface clock select register 0 .................................................................................. 226 scr: iebus communication successful counter ............................................................................. 405 sint0: interrupt timing specification register 0 ................................................................................. 232 sio0: serial i/o shift register 0 ........................................................................................................ 223 sio1: serial i/o shift register 1 ........................................................................................................ 298 sio3: serial i/o shift register 3 ........................................................................................................ 340 ssr: iebus slave status register .................................................................................................... 404 sva0: slave address register 0 ........................................................................................................ 223 [t] tcl50: timer clock select register 50 ................................................................................................ 165 tcl51: timer clock select register 51 ................................................................................................ 165 tm0: 16-bit timer counter 0 ............................................................................................................. 121 tm50: 8-bit timer counter 50 ............................................................................................................. 163 tm51: 8-bit timer counter 51 ............................................................................................................. 163 tmc0: 16-bit timer mode control register 0 ...................................................................................... 124 tmc50: 8-bit timer mode control register 50 ...................................................................................... 166 tmc51: 8-bit timer mode control register 51 ...................................................................................... 166 toc0: 16-bit timer output control register 0 ..................................................................................... 127 txs0: transmit shift register 0 ......................................................................................................... 349 [u] uar: iebus unit address register .................................................................................................... 390 usr: iebus unit status register ....................................................................................................... 396 [v] vm45c: vm45 control register ............................................................................................................. 492 [w] wdcs: watchdog timer clock select register .................................................................................... 190 wdtm: watchdog timer mode register .............................................................................................. 191 558 user? manual u12790ej2v0ud appendix c revision history the revision history of this edition is listed in the table below. ?hapter?indicates the chapter of the previous edition where the revision was made. (1/2) edition revision chapter 2nd addition of pd178096a and 178098a throughout modification of pd178f098 from under development to developed modification of 1.5 development of 8-bit dts series chapter 1 outline modification of pin handing in 2.2.26 v pp ( pd178f098 only) chapter 2 pin modification of table 2-1 pin i/o circuit types and figure 2-1 pin i/o circuits functions addition of description of programming area in 3.1.2 internal data memory space chapter 3 cpu modification of figure 3-10 data to be saved to stack memory and architecture figure 3-11 data to be restored from stack memory modification of [example] in 3.4.4 short direct addressing addition of [illustration] to 3.4.7 based addressing , 3.4.8 based indexed addressing , and 3.4.9 stack addressing addition of description of output latches after reset to 4.4 port function chapter 4 port operations functions 6.2 configuration of 16-bit timer/event counter 0 chapter 6 16-bit addition of cautions to (2) 16-bit capture/compare register 00 (cr00) timer/event addition of table 6-3 cr01 capture trigger and valid edge of ti00 pin counter 0 (crc02 = 1) addition of caution to (3) 16-bit capture/compare register 01 (cr01) addition of caution to figure 6-5 format of prescaler mode register 0 (prm0) 6.4.5 one-shot pulse output operation modification of figure 6-26 timing of one-shot pulse output operation with software trigger addition of note to (2) one-shot pulse output with external trigger addition of 6.5 program list addition of (6) (c) one-shot pulse output function to 6.6 notes on 16-bit timer/event counter 0 7.2 configuration of 8-bit timer/event counters 50, 51 chapter 7 8-bit addition of note to (1) 8-bit timer counters 50 and 51 (tm50 and tm51) timer/event addition of description of pwm mode to (2) 8-bit compare registers 50 and 51 counters (cr50 and cr51) addition of 7.5 program list addition of (4) noise countermeasures and (6) input impedance of ani0 to ani7 chapter 11 a/d pins to 11.5 a/d converter cautions converter addition of figure 16-2 block diagram of baud rate generator chapter 16 serial addition of caution to figure 16-6 permissible error of baud rate allowing interface uart0 for sampling error (k = 0) ( pd178076, 178078, 178f098 only) 559 appendix c revision history user? manual u12790ej2v0ud (2/2) edition revision chapter 2nd addition of caution about inversion of iebus protocol and signal inside the chapter 17 iebus microcontroller to 17.1.6 transfer format of iebus and 17.1.8 bit format controller modification of note and caution in 17.1.6 (9) acknowledge bit ( pd178096a, 178098a, addition of description of lock setting conditions and lock release conditions to 178f098 only) 17.1.7 (4) locking and unlocking addition of description of timing error detection for each period to 17.1.8 bit format addition of notes about automatic master reprocessing to table 17-7 comparison of existing and simple iebus interface functions 17.4.2 description of internal registers ?explanation of each register thoroughly modified and note added ?addition of figures of interrupt timing to figures 17-16 to 17-19 ?addition of figure 17-23 example of broadcast communication flag operation addition of table 17-9 reset conditions of flags in isr register 17.5 interrupt operations of iebus controller thorough modification of contents addition of 17.5.3 communication error source processing list addition of description of wait of slave unit to 17.6.2 master reception correction of description of drive type of eo1 pin in 19.4.1 operation of each chapter 19 pll block of pll frequency synthesizer frequency synthesizer correction of note in table 22-1 hardware status after reset chapter 22 reset function thorough modification of descriptions of flash memory programming as 23.3 flash chapter 23 memory features pd178f098 addition of chapters chapter 25 electrical specifications chapter 26 package drawing chapter 27 recommended soldering conditions thorough modification of descriptions of development tools appendix a deletion of embedded software development tools addition of chapters appendix b register index appendix c revision history |
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